Abstract: An ozone generator (100) includes: a flow path (1) through which gas flows from an inlet (5) to an outlet (6); an ozone generation unit (3) disposed in the flow path (1); and an ozone sensor (4) disposed in the flow path (1) and upstream of the ozone generation unit (3). The flow path (1) has an upstream-side flow path (130) that forms a gas passing space (AR) located upstream of the ozone generation unit (3) and through which the gas flows from one side to another side in a predetermined direction. The inlet (5) is disposed closer to an outer circumferential portion (131) of the upstream-side flow path (130) than the ozone sensor (4).

Abstract: A semiconductor device includes a data bus, a data memory, a selector, a processor, and a debug controller. The selector is configured to be controlled by the debug controller to be in either a first selecting state in which the processor transmits a first signal to the data bus and a second selecting state in which the debug controller transmits a second signal to the data bus. The debug controller is configured to control the state of the selector based on the reception state of a predetermined command from an external device as well as the states of a read enable signal and a write enable signal from the processor such that, when the selector is in the second selecting state, the debug controller accesses the data bus via the selector.

Abstract: It is an object of the present invention to provide a debug system that accesses a semiconductor apparatus from the outside by a simple configuration at less overhead. The present invention relates to a semiconductor apparatus and a debug system. A large scale integration (LSI 11) includes a central processing unit (CPU 20), a debug control portion (21), an internal bus (22), a storage portion (23, 24, 26) connected to the internal bus, and a selector (27). According to a select control signal (CNT) from the CPU, the selector selects either a CPU select state of transmitting a signal from the CPU to the internal bus, or a debugger select state of transmitting a signal from the debug control portion to the internal bus. In principle, the selector is set to the CPU select state.

Abstract: The present disclosure provides a main device, a sub-device and a communication system. The sub-device includes a receiver, a status signal transmitter, a read memory, and a status setting unit. The receiver is configured to receive a read command from the main device. The status signal transmitter is configured to transmit a status signal to the main device. The status setting unit is configured to determine whether a read data has been prepared in the read memory. When the read data has been prepared in the read memory, the status signal is set to a first state. When the read data has not been prepared in the read memory, the status signal is set to a second state.

Abstract: The present disclosure relates to a computing device. A computing device includes an arithmetic processing circuit configured to execute a program, and a program memory for storing the program. Each instruction in the program has a length of 16 bits. The program memory has a first memory area, and a second memory area in which higher addresses than the first memory area are associated. The arithmetic processing circuit has a 16-bit program counter for specifying an address to be read, and reads and executes an instruction at an address corresponding to an upper 15-bit value of the program counter from a target memory area, wherein the target memory area is, of the first memory area and the second memory area, a memory area corresponding to a value of a least significant bit in the program counter.

Abstract: A motor control unit (10) includes, for example, a motor control block (11) that performs feedback control of a drive current that flows through a motor (20) and a machine learning block (14) that analyzes input data including at least the drive current so as to detect a failure level of the motor (20). The motor control block (11) could be configured to dynamically switch a control parameter or a control method in accordance with the failure level. The input data may further include, for example, a drive voltage applied to the motor (20). Furthermore, the input data may further include, for example, at least one of vibrations and a temperature of the motor (20) or a motor device (1) mounting the motor (20) therein.

Abstract: A tracing circuit is integrated in a semiconductor device along with a microprocessor including an m-bit program counter, and externally outputs a tracing clock along with an n-bit tracing data (where 2?n?m). The tracing circuit, when the program counter remains unchanged, synchronously with the tracing clock sets the tracing data to a first output value; when the program counter is incremented, synchronously with the tracing clock sets the tracing data to a second output value; and when the program counter is loaded, synchronously with the tracing clock sets the tracing data to a third output value, and then suspends the state machine in the microprocessor and split-outputs, as the tracing data, the branch destination address or interrupt destination address loaded in the program counter.

Abstract: Provided is a novel heat dissipation structure for a wire harness by which excellent heat dissipation can be ensured while achieving improved versatility using a simple structure. The heat dissipation structure for a wire harness includes wire harnesses, heat dissipation bodies with which the wire harnesses are in contact in a heat conductive manner, and a heat conductive member whose heat conductivity is improved in a specific direction. The wire harnesses and the heat dissipation bodies are pressed against each other with the heat conductive member sandwiched in between in the specific direction.

Abstract: The present invention monitors read data or write data of a CPU without generating any influences on an execution operation of a program. An LSI includes: a processing unit, executing a program; a storage unit, capable of performing a read operation or a write operation; and an internal bus, connected to the processing unit and the storage unit; and a monitoring unit (21). The processing unit is capable of performing a read access or a write access, the read access is outputting a read enable signal (RE) and an address signal (ADD) to the internal bus, and the write access is outputting write data (WD), a write enable signal (WE) and the address signal to the internal bus. The storage unit outputs the read data to the internal bus in response to the read access and stores the write data in response to the write access. The monitoring unit latches the read data or the write data to be sent through the internal bus when an access meeting a set monitoring condition is present.

Abstract: A semiconductor device includes a data bus, a data memory, a selector, a processor, and a debug controller. The selector is configured to be controlled by the debug controller to be in either a first selecting state in which the processor transmits a first signal to the data bus and a second selecting state in which the debug controller transmits a second signal to the data bus. The debug controller is configured to control the state of the selector based on the reception state of a predetermined command from an external device as well as the states of a read enable signal and a write enable signal from the processor such that, when the selector is in the second selecting state, the debug controller accesses the data bus via the selector.

Abstract: A resin joint 20 includes an outer cylinder 21 molded by a resin material capable of transmitting laser light and an inner cylinder 22 disposed facing the inner peripheral surface of the outer cylinder 21. An annular protrusion 22b that protrudes in the radial direction and extends in the circumferential direction is formed on the inner peripheral surface of the outer cylinder 21 or the outer peripheral surface of the inner cylinder 22. The axial end of the resin tube 10 is inserted into an annular space 30 and is deformed in the radial direction following the annular protrusion 22b, and a region deformed in the radial direction has a surface that is in contact with the inner peripheral surface of the outer cylinder 21. The inner peripheral surface of the outer cylinder 21 and the outer peripheral surface of the resin tube 10 are laser-welded.

Abstract: A resin joint 20 includes an outer cylinder 21 molded by a resin material capable of transmitting laser light and an inner cylinder 22 disposed facing the inner peripheral surface of the outer cylinder 21. An annular protrusion 22b that protrudes in the radial direction and extends in the circumferential direction is formed on the inner peripheral surface of the outer cylinder 21 or the outer peripheral surface of the inner cylinder 22. The axial end of the resin tube 10 is inserted into an annular space 30 and is deformed in the radial direction following the annular protrusion 22b, and a region deformed in the radial direction has a surface that is in contact with the inner peripheral surface of the outer cylinder 21. The inner peripheral surface of the outer cylinder 21 and the outer peripheral surface of the resin tube 10 are laser-welded.

Abstract: A microprocessor includes: a first memory bus; a second memory bus; a fetch part configured to fetch an instruction from a first memory connected to the first memory bus; a bus controller configured to control the second memory bus; a determination part configured to determine whether or not an address output from the bus controller is in an area of the first memory; and a first logic circuit part configured to use an output of the determination part to set an access destination of the first memory as the bus controller when the address output from the bus controller is in the area of the first memory.

Abstract: It is an object of the present invention to provide a debug system that accesses a semiconductor apparatus from the outside by a simple configuration at less overhead. The present invention relates to a semiconductor apparatus and a debug system. A large scale integration (LSI 11) includes a central processing unit (CPU 20), a debug control portion (21), an internal bus (22), a storage portion (23, 24, 26) connected to the internal bus, and a selector (27). According to a select control signal (CNT) from the CPU, the selector selects either a CPU select state of transmitting a signal from the CPU to the internal bus, or a debugger select state of transmitting a signal from the debug control portion to the internal bus. In principle, the selector is set to the CPU select state.

Abstract: The present invention monitors read data or write data of a CPU without generating any influences on an execution operation of a program. An LSI includes: a processing unit, executing a program; a storage unit, capable of performing a read operation or a write operation; and an internal bus, connected to the processing unit and the storage unit; and a monitoring unit (21). The processing unit is capable of performing a read access or a write access, the read access is outputting a read enable signal (RE) and an address signal (ADD) to the internal bus, and the write access is outputting write data (WD), a write enable signal (WE) and the address signal to the internal bus. The storage unit outputs the read data to the internal bus in response to the read access and stores the write data in response to the write access. The monitoring unit latches the read data or the write data to be sent through the internal bus when an access meeting a set monitoring condition is present.

Abstract: A microprocessor includes: a first memory bus; a second memory bus; a fetch part configured to fetch an instruction from a first memory connected to the first memory bus; a bus controller configured to control the second memory bus; a determination part configured to determine whether or not an address output from the bus controller is in an area of the first memory; and a first logic circuit part configured to use an output of the determination part to set an access destination of the first memory as the bus controller when the address output from the bus controller is in the area of the first memory.

Abstract: A motor control device includes an energization controller that generates energization control signals of a bridge driver, an ADC that samples and converts analog feedback voltages corresponding to output voltages of the bridge driver into digital feedback signals, and a zero-crossing detector that receives the feedback signals so as to perform zero-crossing detection for determining commutation timing and PWM duty of the energization control signal. Sampling timings of the ADC are switched to one of PWM on period and PWM off period according to the PWM duty. The energization controller PWM drives lower side switches of the bridge driver, and the sampling timings of the ADC are set to the PWM off period. The ADC performs an ADC process of the feedback voltage both in the PWM on period and in the PWM off period, and the zero-crossing detector adopts one of ADC results according to the PWM duty.

Abstract: A quick connector, which can securely demonstrate the lock confirmation function by a checker when a piped body is reinserted, is provided. A checker includes reinsertion-inhibiting bosses. Thus, when a piped body is inserted through an opening of a retainer again in such a state as the checker is moved to the lock confirmation position after the piped body has been pulled from out of a housing and the retainer in such a state as the checker is moved to the release position, the reinsertion-inhibiting bosses hock up onto an annular boss, thereby inhibiting the piped body from being inserted into the retainer and housing.

Abstract: A motor control device includes an energization controller that generates energization control signals of a bridge driver, an ADC that samples and converts analog feedback voltages corresponding to output voltages of the bridge driver into digital feedback signals, and a zero-crossing detector that receives the feedback signals so as to perform zero-crossing detection for determining commutation timing and PWM duty of the energization control signal. Sampling timings of the ADC are switched to one of PWM on period and PWM off period according to the PWM duty. The energization controller PWM drives lower side switches of the bridge driver, and the sampling timings of the ADC are set to the PWM off period. The ADC performs an ADC process of the feedback voltage both in the PWM on period and in the PWM off period, and the zero-crossing detector adopts one of ADC results according to the PWM duty.

Abstract: A quick connector, which can securely demonstrate the lock confirmation function by a checker when a piped body is reinserted, is provided. A checker includes reinsertion-inhibiting bosses. Thus, when a piped body is inserted through an opening of a retainer again in such a state as the checker is moved to the lock confirmation position after the piped body has been pulled from out of a housing and the retainer in such a state as the checker is moved to the release position, the reinsertion-inhibiting bosses hock up onto an annular boss, thereby inhibiting the piped body from being inserted into the retainer and housing.