Abstract: When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.

Abstract: A storage control program for causing a storage control device to perform: receiving, from a higher-level device, an input/output request including a logical address specifying a logical block within a volume; and determining a storage control device for processing the input/output request from among a plurality of storage control devices that may access a storage having a physical storage area assigned to the volume based on the logical address included in the received input/output request, the number of logical blocks per divided block size partitioning the volume, and number of the plurality of storage control devices.

Abstract: A control device includes a processor. The processor is configured to collect plural types of performance information regarding a first data unit. The processor is configured to determine, on basis of the collected plural types of performance information, whether to transfer the first data unit from a first storage device which is under control of a first controller to a second storage device which is positioned as higher than the first storage device. The processor is configured to transfer the first data unit from the first storage device to the second storage device depending on a result of the determination.

Abstract: A control unit stores data used in a process to a shared cache memory. The control unit provides a shared queue in a memory space of the shared cache memory and performs LRU control with the use of the shared queue. The control unit also provides a local queue in the memory space of the shared cache memory. The control unit enqueues a CBE (management information) for a cache page used by a core in a process to the local queue. The control unit dequeues a plurality of CBEs from the local queue upon satisfaction of a predetermined condition, and enqueues the dequeued CBEs to the shared queue.

Abstract: When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.

Abstract: A storage control device is one of a plurality of control devices each controlling different storage areas. The storage control device includes a memory and a processor coupled to the memory. The processor is configured to acquire an allocation request for allocating a storage area to a first virtual volume. The processor is configured to allocate a first storage area to the first virtual volume upon acquiring the allocation request. The first storage area is controlled by a first control device among the plurality of control devices. The first control device controls the first virtual volume.

Abstract: An apparatus includes a first cache memory, a second cache memory, and a processor coupled to the first cache memory and the second cache memory, and configured to store data in the second cache memory, the data being deleted from the first cache memory, store first data stored in a first address of the storage device, in the second cache memory, in case where the first address is included in first management information and is not included in second management information, according to a request for access to the first address of the storage device, the first management information including an address in the storage device of specific data stored in the storage device, and the second management information including an address in the storage device of data stored in both of the second cache memory and the storage device, and register the first address in the second management information.

Abstract: A control device includes a processor. The processor is configured to collect plural types of performance information regarding a first data unit. The processor is configured to determine, on basis of the collected plural types of performance information, whether to transfer the first data unit from a first storage device which is under control of a first controller to a second storage device which is positioned as higher than the first storage device. The processor is configured to transfer the first data unit from the first storage device to the second storage device depending on a result of the determination.

Abstract: An apparatus includes a first cache memory, a second cache memory, and a processor coupled to the first cache memory and the second cache memory, and configured to store data in the second cache memory, the data being deleted from the first cache memory, store first data stored in a first address of the storage device, in the second cache memory, in case where the first address is included in first management information and is not included in second management information, according to a request for access to the first address of the storage device, the first management information including an address in the storage device of specific data stored in the storage device, and the second management information including an address in the storage device of data stored in both of the second cache memory and the storage device, and register the first address in the second management information.

Abstract: A control unit stores data used in a process to a shared cache memory. The control unit provides a shared queue in a memory space of the shared cache memory and performs LRU control with the use of the shared queue. The control unit also provides a local queue in the memory space of the shared cache memory. The control unit enqueues a CBE (management information) for a cache page used by a core in a process to the local queue. The control unit dequeues a plurality of CBEs from the local queue upon satisfaction of a predetermined condition, and enqueues the dequeued CBEs to the shared queue.

Abstract: A storage device that allocates an unused physical storage area to logical storage areas to which write has been requested by an upper device, the storage device including a pattern test unit that tests whether a data pattern written to each of the logical storage areas is a data pattern indicating that allocation of the physical storage area is needed, a skip control unit that determines a skip object for which the pattern test unit does not perform the test among the logical storage areas being test objects of the pattern test unit, and excludes the skip object from the test objects, and a release control unit that releases allocation of a physical storage area to a logical storage area, tested by the pattern test unit, to which the data pattern indicating that allocation of the physical storage area is not needed.

Abstract: Disclosed are a receiving device and a channel estimation method that are capable of using the amplitude information of a received signal to perform proper channel estimation. In the device, a detection section (102) extracts the amplitude information of the OOK modulation signal sequence in which a known CES (Channel Estimation Sequence) composed of data “0” and “1” is OOK (On Off Keying)-modulated to obtain a detected signal sequence. A “1”-detection section (1042) extracts only the sample value corresponding to the data “1” from the sample values of the detected signal sequence to obtain an extracted signal sequence. A correlation calculating section (1043) performs the correlation calculation between the extracted signal sequence and the CES. A propagation delay estimation section (1044) estimates the propagation delay amount of a CIR (Channel Impulse Response) from the correlation calculation.

Abstract: A system can suppress the degradation of the system's own throughput, while suppressing the interference with a different communication system sharing a frequency band with the system. In ST302, a base station selects a terminal (B) as a relay station. In ST305, the base station performs a separation between the subcarrier signals outside an FSS-used band and the subcarrier signals within the FSS-used band, and remaps the separated subcarrier signals within the FSS-used band to the subcarriers outside the FSS-used band. In ST306, the separated subcarrier signals outside the FSS-used band and the remapped subcarrier signals outside the FSS-used band are differentially transmitted at the same time. In ST308, the terminal (B) remaps signals received from the base station to the subcarriers within the FSS-used band and, in ST309, transfers those signals as remapped to a terminal (A).

Abstract: Disclosed are a receiving device and a channel estimation method that are capable of using the amplitude information of a received signal to perform proper channel estimation. In the device, a detection section (102) extracts the amplitude information of the OOK modulation signal sequence in which a known CES (Channel Estimation Sequence) composed of data “0” and “1” is OOK (On Off Keying)-modulated to obtain a detected signal sequence. A “1”-detection section (1042) extracts only the sample value corresponding to the data “1” from the sample values of the detected signal sequence to obtain an extracted signal sequence. A correlation calculating section (1043) performs the correlation calculation between the extracted signal sequence and the CES. A propagation delay estimation section (1044) estimates the propagation delay amount of a CIR (Channel Impulse Response) from the correlation calculation.