Patents by Inventor Takahiro Oikawa

Takahiro Oikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180004907
    Abstract: An abnormality processing system is provided capable of executing appropriate processing in cases where an abnormality occurs in a worker's living body. A management computer 300, if determining that an abnormality is present in a worker's living body, transmits an abnormality signal to an administrator terminal 100, a work device 200, a worker camera 20 and a surveillance camera 50. When receiving the abnormality signal, the administrator terminal 100 displays an image showing that an abnormality has occurred. When receiving the abnormality signal, the work device 200 stops operation. When receiving the abnormality signal, the worker camera 20 and the surveillance camera 50 transmit to the management computer 300 imaging data containing at least data of images before and after a timing at which the abnormality has occurred in the worker's living body.
    Type: Application
    Filed: February 22, 2017
    Publication date: January 4, 2018
    Applicant: OMRON Corporation
    Inventors: Yahiro KOEZUKA, Masahiro TAKAYAMA, Yutaro KATO, Shigeru MATSUI, Hidefumi KONISHI, Hirokazu KASAI, Shigetsugu HIRAKI, Shiko MURAKI, Takamasa KAMEDA, Takahiro OIKAWA
  • Patent number: 9022531
    Abstract: The piezoelectric element includes, on a substrate: a piezoelectric film; and a pair of electrodes provided in contact with the piezoelectric film; in which the piezoelectric film contains a perovskite-type metal oxide represented by the general formula (1) as a main component: Ax(ZnjTi(1-j))l(MgkTi(1-k))mMnO3??General Formula (1) wherein the perovskite-type metal oxide is uniaxially (111)-oriented in pseudo-cubic notation in a thickness direction, of the pair of electrodes, a lower electrode provided on the substrate side is a multilayer electrode including at least a first electrode layer in contact with the substrate and a second electrode layer in contact with the piezoelectric film, and the second electrode layer is a perovskite-type metal oxide electrode which is uniaxially (111)-oriented in pseudo-cubic notation in a thickness direction.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: May 5, 2015
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology, Sophia School Corporation
    Inventors: Makoto Kubota, Kaoru Miura, Hisato Yabuta, Takayuki Watanabe, Jumpei Hayashi, Hiroshi Funakubo, Shintaro Yasui, Takahiro Oikawa, Jun-ichi Nagata, Hiroshi Uchida
  • Patent number: 8907407
    Abstract: The invention prevents a semiconductor device from warping due to heat when it is used. The invention also prevents a formation defect such as peeling of a resist layer used as a plating mask and a formation defect of a front surface electrode. A source pad electrode connected to a source region is formed on a front surface of a semiconductor substrate forming a vertical MOS transistor. A front surface electrode is formed on the source pad electrode by a plating method using a resist layer having openings as a mask. The semiconductor substrate formed with the front surface electrode is thinned by back-grinding. A back surface electrode connected to a drain region is formed on the back surface of the semiconductor substrate. The front surface electrode and the back surface electrode are made of metals having the same coefficients of linear expansion, preferably copper. The front surface electrode and the back surface electrode preferably have the same thicknesses or almost the same thicknesses.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Takahiro Oikawa
  • Patent number: 8669183
    Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: March 11, 2014
    Assignees: SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Akira Suzuki, Katsuyuki Seki, Koujiro Kameyama, Takahiro Oikawa
  • Patent number: 8173543
    Abstract: The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: May 8, 2012
    Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Katsuyuki Seki, Akira Suzuki, Koujiro Kameyama, Takahiro Oikawa
  • Patent number: 8169054
    Abstract: The invention is directed to a semiconductor device having a via hole and a method of manufacturing the same that achieve both the prevention of a barrier layer insufficiently covering the via hole and the control of via resistance at the same time. A semiconductor substrate having a pad electrode on its front surface is prepared. The semiconductor substrate is etched from its back surface to its front surface to form a via hole exposing the pad electrode. A first barrier layer is then formed in the via hole by a sputtering method or a PVD method and reverse-sputtering (etching). By this reverse-sputtering, the barrier layer on the bottom of the via hole is removed to expose the pad electrode. A second barrier layer is then formed on the pad electrode exposed in the via hole. The via resistance is controlled by adjusting only the thickness of the second barrier layer.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: May 1, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Takahiro Oikawa
  • Patent number: 8154129
    Abstract: In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: April 10, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Kikuo Okada, Kojiro Kameyama, Takahiro Oikawa
  • Patent number: 7795115
    Abstract: The invention is directed to enhancement of reliability and a yield of a semiconductor device by a method of manufacturing the semiconductor device with a supporting body without making the process complex. A second insulation film, a semiconductor substrate, a first insulation film, and a passivation film are etched and removed in this order using a resist layer or a protection layer as a mask. By this etching, an adhesive layer is partially exposed in an opening. At this time, a number of semiconductor devices are separated in individual semiconductor dies. Then, as shown in FIG. 10, a solvent (e.g. alcohol or acetone) is supplied to the exposed adhesive layer through the opening to gradually reduce its adhesion and thereby a supporting body is removed from the semiconductor substrate.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: September 14, 2010
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd., Sanyo Semiconductor Manufacturing Co., Ltd.
    Inventors: Koujiro Kameyama, Akira Suzuki, Takahiro Oikawa
  • Patent number: 7781894
    Abstract: The characteristic of the semiconductor device of this invention is that the device has a piercing hole 10 formed in the semiconductor layer to touch a first metal film 18, a insulating film 12 formed on the side wall of the piercing hole 10, a second metal film 13 disposed on the first metal film 18 at the bottom of the piercing hole 10 where the insulating film 12 has not been formed and on the semiconductor layer, a barrier metal film 14 formed on the insulating film 12 in the piercing hole 10 and on the first metal film 18, and a wiring layer 15 formed inside the piercing hole 10 through the barrier metal film 14.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: August 24, 2010
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventor: Takahiro Oikawa
  • Publication number: 20100013008
    Abstract: The invention prevents a semiconductor device from warping due to heat when it is used. The invention also prevents a formation defect such as peeling of a resist layer used as a plating mask and a formation defect of a front surface electrode. A source pad electrode connected to a source region is formed on a front surface of a semiconductor substrate forming a vertical MOS transistor. A front surface electrode is formed on the source pad -electrode by a plating method using a resist layer having openings as a mask. The semiconductor substrate formed with the front surface electrode is thinned by back-grinding. A back surface electrode connected to a drain region is formed on the back surface of the semiconductor substrate. The front surface electrode and the back surface electrode are made of metals having the same coefficients of linear expansion, preferably copper. The front surface electrode and the back surface electrode preferably have the same thicknesses or almost the same thicknesses.
    Type: Application
    Filed: September 30, 2009
    Publication date: January 21, 2010
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventor: Takahiro OIKAWA
  • Publication number: 20090315175
    Abstract: In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.
    Type: Application
    Filed: April 4, 2008
    Publication date: December 24, 2009
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Kikuo Okada, Kojiro Kameyama, Takahiro Oikawa
  • Publication number: 20080023846
    Abstract: The invention provides a method of manufacturing a semiconductor device which achieves high reliability and high yield as well as high production efficiency. Back surface grinding (back grinding) is performed to a semiconductor substrate to thin the semiconductor substrate. A damaged layer formed by the back surface grinding is not removed at this time, and a photoresist layer is selectively formed on the back surface of the semiconductor substrate. The semiconductor substrate is then etched using the photoresist layer as a mask to form a via hole. The photoresist layer is then removed with the semiconductor substrate still placed in an etcher used in the etching process subsequently after the formation of the via hole. In this manner, the etching process and the next ashing process are performed sequentially in one apparatus.
    Type: Application
    Filed: July 26, 2007
    Publication date: January 31, 2008
    Applicants: SANYO ELECTRIC CO., LTD., Sanyo Semiconductor Co., Ltd.
    Inventors: Katsuyuki Seki, Akira Suzuki, Koujiro Kameyama, Takahiro Oikawa
  • Publication number: 20070281474
    Abstract: This invention is directed to form a homogeneous film in a via hole formed in a semiconductor device using Bosch process. The via hole that penetrates through a predetermined region in a semiconductor substrate is formed by etching the semiconductor substrate from one of its surface to the other by the Bosch process using a mask layer as a mask. Next, the mask layer is removed. Then, scallops are removed by dry etching to flatten a sidewall of the via hole. Following the above, an insulation film, a barrier layer and the like are formed homogeneously in the via hole.
    Type: Application
    Filed: May 18, 2007
    Publication date: December 6, 2007
    Applicants: Sanyo Electric Co., Ltd.
    Inventors: Akira Suzuki, Katsuyuki Seki, Koujiro Kameyama, Takahiro Oikawa
  • Publication number: 20070249163
    Abstract: The invention is directed to a semiconductor device having a via hole and a method of manufacturing the same that achieve both the prevention of a barrier layer insufficiently covering the via hole and the control of via resistance at the same time. A semiconductor substrate having a pad electrode on its front surface is prepared. The semiconductor substrate is etched from its back surface to its front surface to form a via hole exposing the pad electrode. A first barrier layer is then formed in the via hole by a sputtering method or a PVD method and reverse-sputtering (etching). By this reverse-sputtering, the barrier layer on the bottom of the via hole is removed to expose the pad electrode. A second barrier layer is then formed on the pad electrode exposed in the via hole. The via resistance is controlled by adjusting only the thickness of the second barrier layer.
    Type: Application
    Filed: April 20, 2007
    Publication date: October 25, 2007
    Applicants: SANYO ELECTRIC CO., LTD., Sanyo Semiconductor Co., Ltd.
    Inventor: Takahiro Oikawa
  • Publication number: 20070166957
    Abstract: The invention is directed to enhancement of reliability and a yield of a semiconductor device by a method of manufacturing the semiconductor device with a supporting body without making the process complex. A second insulation film, a semiconductor substrate, a first insulation film, and a passivation film are etched and removed in this order using a resist layer or a protection layer as a mask. By this etching, an adhesive layer is partially exposed in an opening. At this time, a number of semiconductor devices are separated in individual semiconductor dies. Then, as shown in FIG. 10, a solvent (e.g. alcohol or acetone) is supplied to the exposed adhesive layer through the opening to gradually reduce its adhesion and thereby a supporting body is removed from the semiconductor substrate.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 19, 2007
    Inventors: Koujiro Kameyama, Akira Suzuki, Takahiro Oikawa
  • Publication number: 20070132017
    Abstract: The characteristic of the semiconductor device of this invention is that the device has a piercing hole 10 formed in the semiconductor layer to touch a first metal film 18, a insulating film 12 formed on the side wall of the piercing hole 10, a second metal film 13 disposed on the first metal film 18 at the bottom of the piercing hole 10 where the insulating film 12 has not been formed and on the semiconductor layer, a barrier metal film 14 formed on the insulating film 12 in the piercing hole 10 and on the first metal film 18, and a wiring layer 15 formed inside the piercing hole 10 through the barrier metal film 14.
    Type: Application
    Filed: December 6, 2006
    Publication date: June 14, 2007
    Applicants: SANYO ELECTRIC CO., LTD.
    Inventor: Takahiro Oikawa
  • Patent number: 7230830
    Abstract: In a state wherein front ends of latch members 18A and 18B are apart from each other so that the upper surface of an alignment plate/positioning member 24 is outside, a pressing section 12PU of a heat sink member 12 is brought into contact with the periphery of a semiconductor device 22.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: June 12, 2007
    Assignee: Yamaichi Electronics Co., Ltd.
    Inventors: Ryo Ujike, Takahiro Oikawa, Katsumi Suzuki, Eiji Kobori, Eisaku Tsubota
  • Patent number: 6982410
    Abstract: A photoelectric sensor includes: a light projecting section projecting detection medium light to a detection object region; and a light receiving section receiving reflecting light or transmitted light from the detection object region, the sections being in a single piece or in separate pieces. The light projecting section includes: a light source generating the detection medium light; and a light projecting lens for collimating or collecting the detection medium light from the light source to form a beam spot or a light collecting point in the detection object region. The light projecting section further includes: a deflection angle adjusting unit capable of finely adjusting an optical axis deflection angle of the detection medium light projected to the detection object region from the light projecting section.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: January 3, 2006
    Assignee: Omron Corporation
    Inventors: Takahiro Oikawa, Tadashi Senga
  • Patent number: D532420
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: November 21, 2006
    Assignee: Omron Corporation
    Inventor: Takahiro Oikawa
  • Patent number: D548837
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: August 14, 2007
    Assignee: Omron Corporation
    Inventor: Takahiro Oikawa