Abstract: An infrared sensor substrate includes: column signal lines; row signal lines; a pixel array of pixels including infrared detector elements connected to the column signal lines and the row signal lines. The infrared sensor substrate includes: a current source connected to the infrared detector elements via the column signal lines; a voltage source that applies a voltage to the infrared detector elements via the row signal lines; output terminals connected to the column signal lines, the output terminals being connectable to a signal processing circuit substrate that processes output signals of the infrared detector elements. The infrared sensor substrate includes a monitoring terminal capable of monitoring the voltage applied to the infrared detector elements by the first voltage source.

Abstract: An infrared sensor substrate includes: column signal lines; row signal lines; a pixel array of pixels including infrared detector elements connected to the column signal lines and the row signal lines. The infrared sensor substrate includes: a current source connected to the infrared detector elements via the column signal lines; a voltage source that applies a voltage to the infrared detector elements via the row signal lines; output terminals connected to the column signal lines, the output terminals being connectable to a signal processing circuit substrate that processes output signals of the infrared detector elements. The infrared sensor substrate includes a monitoring terminal capable of monitoring the voltage applied to the infrared detector elements by the first voltage source.

Abstract: An infrared solid-state imaging device with unit detecting sections in a matrix form, wherein the unit detecting section includes: an infrared light guiding layer; a first reflecting layer on the infrared light guiding layer; an infrared light detecting section on the first reflecting layer, the infrared light detecting section including an infrared light absorbing layer and upper and lower contact layers; and first metal wiring connected to the upper contact layer, wherein a side wall of the unit detecting section is inclined at an angle smaller than 45° to a normal direction, to form a groove between the adjacent unit detecting sections, a first insulating layer is provided on the side wall of the unit detecting section and second metal wiring is provided on the first insulating layer, and a refractive index of the first reflecting layer is lower than that of the lower contact layer.

Abstract: In a TDI-type linear image sensor in which pixels are constituted of CCDs (Charge Coupled Devices) of n phases (n being an integer not smaller than 3), a gate opening portion and a gate non-opening portion functioning as a TDI transfer channel (15) are formed in all of transfer gates of the CCDs of n phases constituting the pixels. Within one pixel pitch in a TDI transfer direction, n microlenses (18) are formed such that light is concentrated at the gate non-opening portion formed at the transfer gate of each phase.

Abstract: An infrared solid-state imaging device with unit detecting sections in a matrix form, wherein the unit detecting section includes: an infrared light guiding layer; a first reflecting layer on the infrared light guiding layer; an infrared light detecting section on the first reflecting layer, the infrared light detecting section including an infrared light absorbing layer and upper and lower contact layers; and first metal wiring connected to the upper contact layer, wherein a side wall of the unit detecting section is inclined at an angle smaller than 45° to a normal direction, to form a groove between the adjacent unit detecting sections, a first insulating layer is provided on the side wall of the unit detecting section and second metal wiring is provided on the first insulating layer, and a refractive index of the first reflecting layer is lower than that of the lower contact layer.

Abstract: In a TDI-type linear image sensor in which pixels are constituted of CCDs (Charge Coupled Devices) of n phases (n being an integer not smaller than 3), a gate opening portion and a gate non-opening portion functioning as a TDI transfer channel (15) are formed in all of transfer gates of the CCDs of n phases constituting the pixels. Within one pixel pitch in a TDI transfer direction, n microlenses (18) are formed such that light is concentrated at the gate non-opening portion formed at the transfer gate of each phase.

Abstract: A thermal infrared solid-state imaging device includes a horizontal scanning circuit for scanning a pixel area horizontally to read an infrared image, and vertical scanning circuits provided at both ends of the pixel area. The vertical scanning circuits drive a drive line by applying a driving voltage at both ends of the drive line (in two-end driving). Further a bias voltage is applied at the end of the pixel area to a bias line connected to differential integrating circuits.

Abstract: A thermal infrared imaging device includes a diode, a power supply for supplying a constant power supply voltage to an anode of the diode through a first interconnection, a voltage setting circuit for setting a voltage across the diode, and a current read circuit which is connected to a cathode of the diode through a second interconnection and the voltage setting circuit, for reading a current of the diode. The voltage setting circuit controls a voltage of a connection point of the second interconnection and the voltage setting circuit to a voltage obtained by subtracting a voltage drop from a predetermined bias voltage. The voltage drop is generated by resistances of the first and second interconnections, and the diode current.

Abstract: A thermal infrared solid-state imaging device includes a horizontal scanning circuit for scanning a pixel area horizontally to read an infrared image, and vertical scanning circuits provided at both ends of the pixel area. The vertical scanning circuits drive a drive line by applying a driving voltage at both ends of the drive line (in two-end driving). Further a bias voltage is applied at the end of the pixel area to a bias line connected to differential integrating circuits.

Abstract: A thermal infrared imaging device includes a diode, a power supply for supplying a constant power supply voltage to an anode of the diode through a first interconnection, a voltage setting circuit for setting a voltage across the diode, and a current read circuit which is connected to a cathode of the diode through a second interconnection and the voltage setting circuit, for reading a current of the diode. The voltage setting circuit controls a voltage of a connection point of the second interconnection and the voltage setting circuit to a voltage obtained by subtracting a voltage drop from a predetermined bias voltage. The voltage drop is generated by resistances of the first and second interconnections, and the diode current.

Abstract: A major object is to provide an improved semiconductor device capable of preventing occurrence of a crystal defect in a substrate. A source region is arranged at a surface of a semiconductor substrate and between first and second layered gates. A sidewall spacer is arranged on sidewalls, neighboring to a drain region, of the first and second layered gates. A sidewall spacer is not arranged on sidewalls, neighboring to a source region, of the first and second layered gates.

Abstract: A trench isolating oxide film is formed in a groove formed at a silicon substrate. Floating gate electrodes and control gate electrodes are formed on trench isolating oxide film. An opening exposing the surface of silicon substrate is formed in a region located between the floating gate electrodes and others. The control gate electrodes are covered with a BPTEOS film filling opening. A void is formed within opening filled with BPTEOS film. The void suppresses occurrence of crystal defects in the silicon substrate, and the semiconductor device ensuring high reliability and high yield is obtained.

Abstract: The present invention relates to a non-volatile semiconductor memory device, having the higher margin of the implanted ion passing through a source-to-drain electrode, as well as the excellent covering power of an embedded layer deposited in and above a groove within a field oxide region distributed at both the source-to-drain electrode and a source area. The present invention also provides a method for manufacturing the non-volatile semiconductor memory device.

Abstract: A major object is to provide an improved semiconductor device capable of preventing occurrence of a crystal defect in a substrate.

Abstract: A memory cell array of a nonvolatile semiconductor memory device is provided with a bipolar transistor whose base is connected to a node between sources of two memory cell transistors. A memory cell SL decoder controls the potential level of an emitter of the bipolar transistor. A collector of the bipolar transistor is held at a ground potential. In a read operation, the emitter potential is so controlled that the bipolar transistor enters an ON state, and a current flowing through a channel of either memory cell transistor is amplified by the bipolar transistor to be read.

Abstract: In a nonvolatile semiconductor memory device, a memory cell array includes memory cell transistors and cell select transistors corresponding to the memory cell transistors, respectively. A memory cell SG decoder supplies a potential to a cell select line corresponding to the selected row. The cell select transistor opens and closes a conduction path of a current flowing between a bit line and a source line through the memory cell transistor in accordance with the potential on the cell select line. As a result, an influence by a leak current flowing from the unselected memory cell transistor in a read operation is suppressed.

Abstract: A memory cell transistor connects its drain with a corresponding subbit line. In a program operation, a selected subbit line is connected to a program main bit line. In a read operation, a selected subbit line is connected with the base of a bipolar transistor, so that a channel current of a selected memory cell transistor flows as a base current. The bipolar transistor amplifies this base current, and controls a current flowing through a read main bit line.

Abstract: To a column line to which a selected memory cell is connected, a write bias voltage is supplied through a selection gate transistor having different channel conductivity type than the memory cell transistor. Current drivability of the selection gate transistor is adapted to be larger than a leak current of the memory cell and to supply a current smaller than the channel current when a channel is formed in one aspect. When a verifying voltage is applied to the selected word line, a large channel current flows when a channel is formed, potential of a subbit line is changed accordingly, and programming is suppressed. In another aspect, the selection gate transistor serves as a constant current source to make the programming speed of the memory cells constant. Thus distribution of threshold values after programming can be made narrow.