Abstract: Provided are a solar cell that can be manufactured by non-vacuum process and can have more excellent photoelectric conversion efficiency and a manufacturing method therefor as well as such a semiconductor device and a manufacturing method therefor. A solar cell, includes at least a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes metal oxide particles of 1 nm or more and 500 nm or less in average particle size and a compound having relative permittivity of 2 or more and 1,000 or less. For instance, the content of the organic compound in the first semiconductor layer is 10 mass % or more and 90 mass % or less.

Abstract: Provided are a solar cell that can be manufactured by non-vacuum process and can have more excellent photoelectric conversion efficiency and a manufacturing method therefor as well as such a semiconductor device and a manufacturing method therefor. A solar cell, includes at least a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes metal oxide particles of 1 nm or more and 500 nm or less in average particle size and a compound having relative permittivity of 2 or more and 1,000 or less. For instance, the content of the organic compound in the first semiconductor layer is 10 mass % or more and 90 mass % or less.

Abstract: Provided are a solar cell that can be manufactured by non-vacuum process and can have more excellent photoelectric conversion efficiency and a manufacturing method therefor as well as such a semiconductor device and a manufacturing method therefor. A solar cell, includes at least a first semiconductor layer (140) and a second semiconductor layer (130). The first semiconductor layer (140) includes metal oxide particles of 1 nm or more and 500 nm or less in average particle size and a compound having relative permittivity of 2 or more and 1,000 or less. For instance, the content of the organic compound in the first semiconductor layer (140) is 10 mass % or more and 90 mass % or less.

Abstract: Provided are a solar cell that can be manufactured by non-vacuum process and can have more excellent photoelectric conversion efficiency and a manufacturing method therefor as well as such a semiconductor device and a manufacturing method therefor. A solar cell, includes at least a first semiconductor layer (140) and a second semiconductor layer (130). The first semiconductor layer (140) includes metal oxide particles of 1 nm or more and 500 nm or less in average particle size and a compound having relative permittivity of 2 or more and 1,000 or less. For instance, the content of the organic compound in the first semiconductor layer (140) is 10 mass % or more and 90 mass % or less.

Abstract: A semiconductor memory includes a plurality of memory cells, a refresh request generator circuit for generating a refresh request signal to refresh the plurality of memory cells based on a number of clock cycles elapsed in a clock signal, a clock cycle detector circuit for detecting the clock cycle of the clock signal, and a refresh controller circuit for controlling a number of memory cells to refresh from among the plurality of memory cells, in accordance with the detected clock cycle.

Abstract: A semiconductor integrated circuit, including a data input unit for receiving an input data signal to be supplied to an external data input terminal, a storage unit for storing the input data signal received by the data input unit, a timing generating unit for generating a timing signal in response to an output request signal, a data output unit for outputting, in synchronization with the timing signal, the input data signal stored in the storage unit as an output data signal, a test output control unit for outputting, in synchronization with the timing signal, and a data selector for outputting the output data signal supplied from the data output unit to the external data output terminal in a normal operation mode and outputting the input data signal supplied from the test output control unit to the external data output terminal in a test mode.

Abstract: A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

Abstract: A semiconductor memory includes a plurality of memory cells, a refresh request generator circuit for generating a refresh request signal to refresh the plurality of memory cells based on a number of clock cycles elapsed in a clock signal, a clock cycle detector circuit for detecting the clock cycle of the clock signal, and a refresh controller circuit for controlling a number of memory cells to refresh from among the plurality of memory cells, in accordance with the detected clock cycle.

Abstract: A semiconductor integrated circuit, including a data input unit for receiving an input data signal to be supplied to an external data input terminal, a storage unit for storing the input data signal received by the data input unit, a timing generating unit for generating a timing signal in response to an output request signal, a data output unit for outputting, in synchronization with the timing signal, the input data signal stored in the storage unit as an output data signal, a test output control unit for outputting, in synchronization with the timing signal, and a data selector for outputting the output data signal supplied from the data output unit to the external data output terminal in a normal operation mode and outputting the input data signal supplied from the test output control unit to the external data output terminal in a test mode.

Abstract: A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

Abstract: A word control circuit activates word lines corresponding to a start row address and a next row address overlapping in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

Abstract: A word control circuit activates word lines corresponding to a start row address and a next row address overlapping in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

Abstract: A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

Abstract: A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

Abstract: A semiconductor memory device having a plurality of pair cells including a pair of cells for storing ordinary data and auxiliary data in which the operation of one cell in a pair cell can be checked. At normal operation time data can be read from or written to a desired cell by activating two word lines at a time. On the other hand, at operation test time data can be read from or written to only one cell in a pair cell by activating a desired word line.

Abstract: A semiconductor memory device having a plurality of pair cells including a pair of cells for storing ordinary data and auxiliary data in which the operation of one cell in a pair cell can be checked. At normal operation time data can be read from or written to a desired cell by activating two word lines at a time. On the other hand, at operation test time data can be read from or written to only one cell in a pair cell by activating a desired word line.

Abstract: A semiconductor integrated circuit includes a gate extending in a first direction, a diffusion-layer region corresponding to the gate, and a plurality of backing wiring lines connected to the diffusion-layer region and extending in a first wiring layer in a second direction substantially perpendicular to the first direction. The semiconductor integrated circuit further includes connection wiring lines providing connections between the plurality of backing wiring lines and provided in a second wiring layer.