Patents by Inventor Takahiro Sonoda
Takahiro Sonoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6549484Abstract: An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.Type: GrantFiled: September 28, 2001Date of Patent: April 15, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Sadayuki Morita, Takeshi Sakata, Satoru Hanzawa, Takahiro Sonoda, Haruko Tadokoro, Hiroshi Ichikawa, Osamu Nagashima
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Publication number: 20030002316Abstract: A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.Type: ApplicationFiled: August 30, 2002Publication date: January 2, 2003Inventors: Sadayuki Morita, Takeshi Sakata, Satoru Hanzawa, Takahiro Sonoda, Haruko Tadokoro, Hiroshi Ichikawa, Osamu Nagashima
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Publication number: 20020118575Abstract: A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.Type: ApplicationFiled: April 12, 2002Publication date: August 29, 2002Applicant: Hitachi, Ltd.Inventors: Takahiro Sonoda, Takeshi Sakata, Sadayuki Morita, Yoshinobu Nakagome, Haruko Tadokoro, Osamu Nagashima
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Patent number: 6407963Abstract: A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.Type: GrantFiled: October 13, 2000Date of Patent: June 18, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., LtdInventors: Takahiro Sonoda, Takeshi Sakata, Sadayuki Morita, Yoshinobu Nakagome, Haruko Tadokoro, Osamu Nagashima
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Publication number: 20020018396Abstract: An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.Type: ApplicationFiled: September 28, 2001Publication date: February 14, 2002Inventors: Sadayuki Morita, Takeshi Sakata, Satoru Hanzawa, Takahiro Sonoda, Haruko Tadokoro, Hiroshi Ichikawa, Osamu Nagashima
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Publication number: 20020009006Abstract: By using a few number of needles and a few number of contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A MCP having a packaging structure in which a volatile SRAM semiconductor chip and a nonvolatile flash memory semiconductor chip are formed is assembled in accordance with steps S201 to S212 by performing burn-in of each semiconductor chip of the SRAM and the flash memory under the state of a semiconductor wafer, and by forming the good SRAM to be subjected to burn-in and the flash memory semiconductor chip. At this burn-in, contact check is performed by bringing a needle provided in a burn-in board, into contact with six test-only signal terminals of a test circuit formed on each semiconductor chip.Type: ApplicationFiled: July 17, 2001Publication date: January 24, 2002Inventors: Yoshikazu Saitoh, Sadayuki Morita, Takahiro Sonoda
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Patent number: 6335901Abstract: An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.Type: GrantFiled: March 20, 2000Date of Patent: January 1, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Sadayuki Morita, Takeshi Sakata, Satoru Hanzawa, Takahiro Sonoda, Haruko Tadokoro, Hiroshi Ichikawa, Osamu Nagashima
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Patent number: 6271687Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on a small voltage difference of input signals being amplified in two stages and the amplifying circuit being 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.Type: GrantFiled: March 21, 2000Date of Patent: August 7, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita
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Patent number: 6046609Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.Type: GrantFiled: November 10, 1998Date of Patent: April 4, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita
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Patent number: 5936909Abstract: A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address selection circuit selects a memory cell in one of the memory mats, and connects the selected memory cell to a sense amplifier or a write amplifier furnished corresponding to the memory mat in question. At the same time, an address counter generates an address signal corresponding to the address signal by which one of the memory mats has been selected. When a burst mode is designated by a control signal, the address signal admitted to the address register is used to select a memory cell in a first memory mat. The selected memory cell is connected to the corresponding sense amplifier or write amplifier.Type: GrantFiled: January 27, 1998Date of Patent: August 10, 1999Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Takahiro Sonoda, Sadayuki Morita, Hirofumi Zushi, Haruko Kawachino, Hideharu Yahata, Kenichi Fukui, Tomohiro Nagano, Masashige Harada
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Patent number: 5854562Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.Type: GrantFiled: April 15, 1997Date of Patent: December 29, 1998Assignees: Hitachi, Ltd, Hitachi ULSI Engineering Corp.Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita