Patents by Inventor Takahiro Sugimura
Takahiro Sugimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250070093Abstract: A power module includes a first board comprising a first surface and a second surface opposite to each other and perpendicular to a bottom surface of the power module for mounting the power module to a circuit board, the bottom surface providing electrical connections to the circuit board, a first charge pump assembly mounted on the first surface, the first charge pump assembly comprising a first power conversion circuit configured to convert an input voltage to an output voltage, and a first vertical heatsink structure arranged adjacent to the first charge pump assembly, the first charge pump assembly being placed between the first vertical heatsink structure and the first board.Type: ApplicationFiled: November 12, 2024Publication date: February 27, 2025Inventors: Laurence McGarry, Michael Patrick Clark, Takahiro Sugimura, David Giuliano
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Patent number: 8896114Abstract: A semiconductor device includes a semiconductor chip, a die pad having a chip mount surface for mounting the semiconductor chip, and an electrode terminal for connecting with the semiconductor chip through first and second wirings. The electrode terminal has a first surface including a connection point with the first wiring and a second surface including a connection point with the second wiring. The connection point with the first wiring is located at a first height from a reference plane extending from the chip mount surface. The connection point with the second wiring is located at a second height different from the first height from the reference plane.Type: GrantFiled: March 14, 2013Date of Patent: November 25, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiroshi Notsu, Takahiro Sugimura
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Publication number: 20130270706Abstract: A semiconductor device according to an embodiment includes: first and second semiconductor chips, each including a first electrode and a second electrode opposite to each other in a predetermined direction; a chip-mount substrate on which the first and second semiconductor chips are mounted; and a first wiring terminal to which the second electrodes of the first and second semiconductor chips are connected. The second semiconductor chip lies over the first semiconductor chip in the predetermined direction such that the second electrode of the first semiconductor chip and the second electrode of the second semiconductor chip face each other across the first wiring terminal, and the chip-mount substrate is bent such that the first electrode of the first semiconductor chip is connected to the first electrode of the second semiconductor chip.Type: ApplicationFiled: March 28, 2013Publication date: October 17, 2013Applicant: Sumitomo Electric Industries, Ltd.Inventors: Takahiro Sugimura, Hiroshi Notsu
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Publication number: 20130264697Abstract: A semiconductor device includes a semiconductor chip, a die pad having a chip mount surface for mounting the semiconductor chip, and an electrode terminal for connecting with the semiconductor chip through first and second wirings. The electrode terminal has a first surface including a connection point with the first wiring and a second surface including a connection point with the second wiring. The connection point with the first wiring is located at a first height from a reference plane extending from the chip mount surface. The connection point with the second wiring is located at a second height different from the first height from the reference plane.Type: ApplicationFiled: March 14, 2013Publication date: October 10, 2013Applicant: Sumitomo Electric Industries, Ltd.Inventors: Hiroshi Notsu, Takahiro Sugimura
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Publication number: 20130256920Abstract: A semiconductor device in one embodiment includes a chip-mount substrate, a first semiconductor chip mounted on the chip-mount substrate, and a second semiconductor chip mounted adjacent to the first semiconductor chip on the chip-mount substrate. The chip-mount substrate has a first surface on which the first semiconductor chip is mounted, and a second surface on which the second semiconductor chip is mounted. The second surface and the first surface are at different positions in a thickness direction of the chip-mount substrate.Type: ApplicationFiled: March 28, 2013Publication date: October 3, 2013Applicant: Sumitomo Electric Industries, Ltd.Inventors: Takahiro Sugimura, Hiroshi Notsu
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Publication number: 20130249008Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, a gate electrode terminal, and a die pad. The first semiconductor chip has a first gate electrode pad and a second gate electrode pad electrically connected to the first gate electrode pad. The second semiconductor chip has a gate electrode pad connected to the second gate electrode pad via a wiring. The gate electrode terminal is connected to the first gate electrode pad of the first semiconductor chip via a wiring. The die pad has a chip mounting surface for mounting the first and second semiconductor chips.Type: ApplicationFiled: February 26, 2013Publication date: September 26, 2013Applicant: Sumitomo Electric Industries, Ltd.Inventors: Takahiro SUGIMURA, Hiroshi NOTSU
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Publication number: 20120306086Abstract: A semiconductor device according to an embodiment includes an insulating substrate, a wiring layer formed on a first main surface of the insulating substrate, and a semiconductor element mounted on the wiring layer. In this semiconductor device, the wiring layer includes a first copper-containing material containing copper and a metal having the thermal expansion coefficient smaller than that of copper and the thermal expansion coefficient of the first copper-containing material is smaller than that of copper.Type: ApplicationFiled: May 31, 2012Publication date: December 6, 2012Applicant: Sumitomo Electric Industries, Ltd.Inventors: Takahiro Sugimura, Takashi Tsuno
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Patent number: 8101468Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: GrantFiled: October 18, 2010Date of Patent: January 24, 2012Assignee: Renesas Electronics CorporationInventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Publication number: 20110033983Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: ApplicationFiled: October 18, 2010Publication date: February 10, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Patent number: 7838335Abstract: The adhesive property of the mold resin exposed to the ball face side of a semiconductor package and under-filling resin is improved, and the manufacturing method of the semiconductor device which can prevent peeling at both interface is obtained. The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper part after the sputtering step, and the step fills up with under-filling resin between the semiconductor package and the wiring substrate are included.Type: GrantFiled: November 10, 2008Date of Patent: November 23, 2010Assignee: Renesas Electronics CorporationInventors: Eiji Hayashi, Takahiro Sugimura
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Patent number: 7834455Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: GrantFiled: May 22, 2009Date of Patent: November 16, 2010Assignee: Renesas Electronics CorporationInventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Publication number: 20090230551Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: ApplicationFiled: May 22, 2009Publication date: September 17, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Patent number: 7547968Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2 , and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: GrantFiled: May 17, 2006Date of Patent: June 16, 2009Assignee: Renesas Technology Corp.Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Publication number: 20090075425Abstract: The adhesive property of the mold resin exposed to the ball face side of a semiconductor package and under-filling resin is improved, and the manufacturing method of the semiconductor device which can prevent peeling at both interface is obtained. The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper part after the sputtering step, and the step fills up with under-filling resin between the semiconductor package and the wiring substrate are included.Type: ApplicationFiled: November 10, 2008Publication date: March 19, 2009Inventors: Eiji Hayashi, Takahiro Sugimura
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Patent number: 7459342Abstract: The adhesive property of the mold resin exposed to the ball face side of a semiconductor package and under-filling resin is improved, and the manufacturing method of the semiconductor device which can prevent peeling at both interface is obtained. The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper part after the sputtering step, and the step fills up with under-filling resin between the semiconductor package and the wiring substrate are included.Type: GrantFiled: December 29, 2006Date of Patent: December 2, 2008Assignee: Renesas Technology Corp.Inventors: Eiji Hayashi, Takahiro Sugimura
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Publication number: 20080036083Abstract: The semiconductor device which can prevent destruction of a low dielectric constant film and a bump's destruction which consists of lead free solder both is obtained. A semiconductor package which has a semiconductor chip including a low dielectric constant film and a bump which consists of lead free solder, a wiring substrate by which flip chip junction of the semiconductor package was done via the bump, and under-filling resin, with which a gap between the semiconductor package and the wiring substrate is filled up, are provided. As for under-filling resin, the glass transition temperature is equal to or more than 125° C., the coefficient of thermal expansion in 125° C. is less than 40 ppm/° C., and the elastic modulus in 25° C. is less than 9 GPa.Type: ApplicationFiled: August 3, 2007Publication date: February 14, 2008Inventors: Yuko Sawada, Shinji Baba, Takahiro Sugimura
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Publication number: 20070196955Abstract: The adhesive property of the mold resin exposed to the ball face side of a semiconductor package and under-filling resin is improved, and the manufacturing method of the semiconductor device which can prevent peeling at both interface is obtained. The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper part after the sputtering step, and the step fills up with under-filling resin between the semiconductor package and the wiring substrate are included.Type: ApplicationFiled: December 29, 2006Publication date: August 23, 2007Inventors: Eiji HAYASHI, Takahiro Sugimura
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Publication number: 20060264022Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.Type: ApplicationFiled: May 17, 2006Publication date: November 23, 2006Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
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Publication number: 20060094806Abstract: An aqueous emulsion based pressure sensitive adhesive is disclosed that includes water and a water dispersible polymer, and has (1) a viscosity of 100 to 1000 mPa·s, (2) a dynamic surface tension of a water diluted 75% solution thereof of 59 mN/m or more at a discharge frequency of 25 Hz and a temperature of 25° C., and (3) a nonvolatile content of 50 to 70 wt %. This pressure sensitive adhesive is an emulsion composition having low viscosity and ease of handling and causing no coating defects such as ‘cissing’ and ‘retraction’ when coated on a release paper. Furthermore, there is disclosed a process for producing a pressure sensitive adhesive sheet that includes a release material, a pressure sensitive adhesive layer, and a substrate, the pressure sensitive adhesive layer being formed from the above aqueous emulsion based pressure sensitive adhesive.Type: ApplicationFiled: December 19, 2005Publication date: May 4, 2006Applicant: Toyo Ink Mfg. Co., Ltd.Inventors: Masayoshi Matsumoto, Takahiro Sugimura
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Publication number: 20030212195Abstract: An aqueous emulsion based pressure sensitive adhesive is disclosed that includes water and a water dispersible polymer, and has (1) a viscosity of 100 to 1000 mpa·s, (2) a dynamic surface tension of a water diluted 75% solution thereof of 59 mN/m or more at a discharge frequency of 25 Hz and a temperature of 25° C., and (3) a nonvolatile content of 50 to 70 wt %. This pressure sensitive adhesive is an emulsion composition having low viscosity and ease of handling and causing no coating defects such as ‘cissing’ and ‘retraction’ when coated on a release paper.Type: ApplicationFiled: May 13, 2003Publication date: November 13, 2003Applicant: Toyo Ink Mfg. Co., Ltd.Inventors: Masayoshi Matsumoto, Takahiro Sugimura