Patents by Inventor Takahiro Sugimura

Takahiro Sugimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8896114
    Abstract: A semiconductor device includes a semiconductor chip, a die pad having a chip mount surface for mounting the semiconductor chip, and an electrode terminal for connecting with the semiconductor chip through first and second wirings. The electrode terminal has a first surface including a connection point with the first wiring and a second surface including a connection point with the second wiring. The connection point with the first wiring is located at a first height from a reference plane extending from the chip mount surface. The connection point with the second wiring is located at a second height different from the first height from the reference plane.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Notsu, Takahiro Sugimura
  • Publication number: 20130270706
    Abstract: A semiconductor device according to an embodiment includes: first and second semiconductor chips, each including a first electrode and a second electrode opposite to each other in a predetermined direction; a chip-mount substrate on which the first and second semiconductor chips are mounted; and a first wiring terminal to which the second electrodes of the first and second semiconductor chips are connected. The second semiconductor chip lies over the first semiconductor chip in the predetermined direction such that the second electrode of the first semiconductor chip and the second electrode of the second semiconductor chip face each other across the first wiring terminal, and the chip-mount substrate is bent such that the first electrode of the first semiconductor chip is connected to the first electrode of the second semiconductor chip.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 17, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takahiro Sugimura, Hiroshi Notsu
  • Publication number: 20130264697
    Abstract: A semiconductor device includes a semiconductor chip, a die pad having a chip mount surface for mounting the semiconductor chip, and an electrode terminal for connecting with the semiconductor chip through first and second wirings. The electrode terminal has a first surface including a connection point with the first wiring and a second surface including a connection point with the second wiring. The connection point with the first wiring is located at a first height from a reference plane extending from the chip mount surface. The connection point with the second wiring is located at a second height different from the first height from the reference plane.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 10, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Notsu, Takahiro Sugimura
  • Publication number: 20130256920
    Abstract: A semiconductor device in one embodiment includes a chip-mount substrate, a first semiconductor chip mounted on the chip-mount substrate, and a second semiconductor chip mounted adjacent to the first semiconductor chip on the chip-mount substrate. The chip-mount substrate has a first surface on which the first semiconductor chip is mounted, and a second surface on which the second semiconductor chip is mounted. The second surface and the first surface are at different positions in a thickness direction of the chip-mount substrate.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 3, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takahiro Sugimura, Hiroshi Notsu
  • Publication number: 20130249008
    Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, a gate electrode terminal, and a die pad. The first semiconductor chip has a first gate electrode pad and a second gate electrode pad electrically connected to the first gate electrode pad. The second semiconductor chip has a gate electrode pad connected to the second gate electrode pad via a wiring. The gate electrode terminal is connected to the first gate electrode pad of the first semiconductor chip via a wiring. The die pad has a chip mounting surface for mounting the first and second semiconductor chips.
    Type: Application
    Filed: February 26, 2013
    Publication date: September 26, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takahiro SUGIMURA, Hiroshi NOTSU
  • Publication number: 20120306086
    Abstract: A semiconductor device according to an embodiment includes an insulating substrate, a wiring layer formed on a first main surface of the insulating substrate, and a semiconductor element mounted on the wiring layer. In this semiconductor device, the wiring layer includes a first copper-containing material containing copper and a metal having the thermal expansion coefficient smaller than that of copper and the thermal expansion coefficient of the first copper-containing material is smaller than that of copper.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 6, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takahiro Sugimura, Takashi Tsuno
  • Patent number: 8101468
    Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: January 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
  • Publication number: 20110033983
    Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.
    Type: Application
    Filed: October 18, 2010
    Publication date: February 10, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
  • Patent number: 7838335
    Abstract: The adhesive property of the mold resin exposed to the ball face side of a semiconductor package and under-filling resin is improved, and the manufacturing method of the semiconductor device which can prevent peeling at both interface is obtained. The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper part after the sputtering step, and the step fills up with under-filling resin between the semiconductor package and the wiring substrate are included.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: November 23, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Hayashi, Takahiro Sugimura
  • Patent number: 7834455
    Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: November 16, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
  • Publication number: 20090230551
    Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.
    Type: Application
    Filed: May 22, 2009
    Publication date: September 17, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
  • Patent number: 7547968
    Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2 , and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: June 16, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
  • Publication number: 20090075425
    Abstract: The adhesive property of the mold resin exposed to the ball face side of a semiconductor package and under-filling resin is improved, and the manufacturing method of the semiconductor device which can prevent peeling at both interface is obtained. The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper part after the sputtering step, and the step fills up with under-filling resin between the semiconductor package and the wiring substrate are included.
    Type: Application
    Filed: November 10, 2008
    Publication date: March 19, 2009
    Inventors: Eiji Hayashi, Takahiro Sugimura
  • Patent number: 7459342
    Abstract: The adhesive property of the mold resin exposed to the ball face side of a semiconductor package and under-filling resin is improved, and the manufacturing method of the semiconductor device which can prevent peeling at both interface is obtained. The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper part after the sputtering step, and the step fills up with under-filling resin between the semiconductor package and the wiring substrate are included.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: December 2, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Eiji Hayashi, Takahiro Sugimura
  • Publication number: 20080036083
    Abstract: The semiconductor device which can prevent destruction of a low dielectric constant film and a bump's destruction which consists of lead free solder both is obtained. A semiconductor package which has a semiconductor chip including a low dielectric constant film and a bump which consists of lead free solder, a wiring substrate by which flip chip junction of the semiconductor package was done via the bump, and under-filling resin, with which a gap between the semiconductor package and the wiring substrate is filled up, are provided. As for under-filling resin, the glass transition temperature is equal to or more than 125° C., the coefficient of thermal expansion in 125° C. is less than 40 ppm/° C., and the elastic modulus in 25° C. is less than 9 GPa.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 14, 2008
    Inventors: Yuko Sawada, Shinji Baba, Takahiro Sugimura
  • Publication number: 20070196955
    Abstract: The adhesive property of the mold resin exposed to the ball face side of a semiconductor package and under-filling resin is improved, and the manufacturing method of the semiconductor device which can prevent peeling at both interface is obtained. The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper part after the sputtering step, and the step fills up with under-filling resin between the semiconductor package and the wiring substrate are included.
    Type: Application
    Filed: December 29, 2006
    Publication date: August 23, 2007
    Inventors: Eiji HAYASHI, Takahiro Sugimura
  • Publication number: 20060264022
    Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2, and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.
    Type: Application
    Filed: May 17, 2006
    Publication date: November 23, 2006
    Inventors: Takahiro Sugimura, Satoshi Imasu, Norihiko Sugita, Takafumi Betsui
  • Publication number: 20060094806
    Abstract: An aqueous emulsion based pressure sensitive adhesive is disclosed that includes water and a water dispersible polymer, and has (1) a viscosity of 100 to 1000 mPa·s, (2) a dynamic surface tension of a water diluted 75% solution thereof of 59 mN/m or more at a discharge frequency of 25 Hz and a temperature of 25° C., and (3) a nonvolatile content of 50 to 70 wt %. This pressure sensitive adhesive is an emulsion composition having low viscosity and ease of handling and causing no coating defects such as ‘cissing’ and ‘retraction’ when coated on a release paper. Furthermore, there is disclosed a process for producing a pressure sensitive adhesive sheet that includes a release material, a pressure sensitive adhesive layer, and a substrate, the pressure sensitive adhesive layer being formed from the above aqueous emulsion based pressure sensitive adhesive.
    Type: Application
    Filed: December 19, 2005
    Publication date: May 4, 2006
    Applicant: Toyo Ink Mfg. Co., Ltd.
    Inventors: Masayoshi Matsumoto, Takahiro Sugimura
  • Publication number: 20030212195
    Abstract: An aqueous emulsion based pressure sensitive adhesive is disclosed that includes water and a water dispersible polymer, and has (1) a viscosity of 100 to 1000 mpa·s, (2) a dynamic surface tension of a water diluted 75% solution thereof of 59 mN/m or more at a discharge frequency of 25 Hz and a temperature of 25° C., and (3) a nonvolatile content of 50 to 70 wt %. This pressure sensitive adhesive is an emulsion composition having low viscosity and ease of handling and causing no coating defects such as ‘cissing’ and ‘retraction’ when coated on a release paper.
    Type: Application
    Filed: May 13, 2003
    Publication date: November 13, 2003
    Applicant: Toyo Ink Mfg. Co., Ltd.
    Inventors: Masayoshi Matsumoto, Takahiro Sugimura