Patents by Inventor Takahiro Tabira

Takahiro Tabira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11355515
    Abstract: Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: June 7, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naoto Hojo, Takahiro Tabira, Yoshitaka Otsu
  • Publication number: 20200286916
    Abstract: Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Inventors: Naoto Hojo, Takahiro Tabira, Yoshitaka Otsu
  • Patent number: 10700089
    Abstract: Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: June 30, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naoto Hojo, Takahiro Tabira, Yoshitaka Otsu
  • Patent number: 9559058
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: January 31, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaki Haneda, Michie Sunayama, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Takahiro Tabira
  • Publication number: 20120181695
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Application
    Filed: March 29, 2012
    Publication date: July 19, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaki HANEDA, Michie SUNAYAMA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Takahiro TABIRA
  • Patent number: 8168532
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: May 1, 2012
    Assignee: Fujitsu Limited
    Inventors: Masaki Haneda, Michie Sunayama, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Takahiro Tabira
  • Patent number: 8067836
    Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masaki Haneda, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Michie Sunayama, Takahiro Tabira
  • Publication number: 20090321937
    Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.
    Type: Application
    Filed: April 29, 2009
    Publication date: December 31, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Masaki HANEDA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Michie SUNAYAMA, Takahiro TABIRA
  • Publication number: 20090121355
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Application
    Filed: November 10, 2008
    Publication date: May 14, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Masaki HANEDA, Michie SUNAYAMA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Takahiro TABIRA