Patents by Inventor Takahiro Takeuchi

Takahiro Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105424
    Abstract: A first RF pulse signal includes a plurality of main cycles. Each main cycle includes first and second durations. The first duration includes a plurality of first sub cycles, and the second duration includes a plurality of second sub cycles. The first RF pulse signal has three or more different power levels in each of the plurality of first sub cycles and the plurality of second sub cycles. A second RF pulse signal including a plurality of main cycles. The second RF pulse signal has two or more different power levels in each of the plurality of first sub cycles and a zero power level in the second duration. A third RF pulse signal includes a plurality of main cycles. The third RF pulse signal has two or more different power levels in each of the plurality of first sub cycles and a zero power level in the second duration.
    Type: Application
    Filed: December 8, 2023
    Publication date: March 28, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Takahiro TAKEUCHI, Masahiko TAKAHASHI, Ken KOBAYASHI
  • Publication number: 20240092645
    Abstract: A silica particle includes: a quaternary ammonium salt, in which the following expressions are satisfied, 0.90?FBEFORE/FAFTER?1.10, and 5?FSINTERING/FBEFORE?20, in which FBEFORE represents a maximum frequency value of a pore diameter of 2 nm or less in the silica particles before washing, which is obtained from a pore distribution curve in a nitrogen gas adsorption method, FAFTER represents a maximum frequency value of the pore diameter of 2 nm or less in the silica particles after washing, which is obtained from the pore distribution curve in the nitrogen gas adsorption method, and FSINTERING represents a maximum frequency value of the pore diameter of 2 nm or less in the silica particles before washing and after sintering at 600° C., which is obtained from the pore distribution curve in the nitrogen gas adsorption method.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: FUJIFILM Business Innovation Corp.
    Inventors: Yuka Zenitani, Koji Sasaki, Sakae Takeuchi, Yoshifumi Eri, Takahiro Mizuguchi
  • Publication number: 20240083409
    Abstract: A vehicle including: a battery; a voltage control unit that boosts an output voltage of the battery; a main drive unit, including an engine and a main drive motor driven by electric power with a boosted voltage, that outputs a main driving force for driving one of a front wheel and a rear wheel by at least one of the engine and the main drive motor; a sub drive unit, including a sub drive motor driven by the electric power with the boosted voltage, that outputs a sub driving force for driving another of the front wheel and the rear wheel; and a control unit, in which, when a temperature of the sub drive unit makes equal to or higher than a predetermined value while the main drive unit outputs the main driving force including a driving force of the engine, the control unit increases the boosted voltage.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 14, 2024
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Takahiro KOZEKI, Takuya HONJO, Daisuke TAKEUCHI
  • Patent number: 11906870
    Abstract: According to one embodiment, a display device includes a first conductive layer, a second conductive layer overlapping the first conductive layer, a first capacitive portion located in a same layer as the first conductive layer, a second capacitive portion located in a same layer as the second conductive layer and overlapping the first capacitive portion, a first inorganic insulating film located between the first conductive layer and the second conductive layer and between the first capacitive portion and the second capacitive portion, a drain electrode electrically connected to the second capacitive portion, a pixel electrode electrically connected to the drain electrode.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: February 20, 2024
    Assignee: Japan Display Inc.
    Inventors: Koji Ishizaki, Yoshitaka Ozeki, Takahiro Takeuchi, Koshiro Moriguchi, Tomoyasu Hirano
  • Publication number: 20240014006
    Abstract: A plasma processing apparatus includes: a plasma processing apparatus includes: a plasma processing chamber; a substrate support; a source RF generator coupled to the plasma processing chamber, and configured to generate a source RF pulsed signal; a first bias RF generator configured to generate a first bias RF pulsed signal; a second bias RF generator configured to generate a second bias RF pulsed signal; a first separation circuit connected between the first bias RF generator and the substrate support, and configured to suppress a coupling of the second bias RF pulsed signal from the second bias RF generator to the first bias RF generator, and a second separation circuit connected between the second bias RF generator and the substrate support, and configured to suppress a coupling of the first bias RF pulsed signal from the first bias RF generator to the second bias RF generator.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 11, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Naoki FUJIWARA, Mitsunori OHATA, Takahiro TAKEUCHI
  • Publication number: 20230397449
    Abstract: A detection apparatus includes: a substrate; photodiodes each including a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer; transistors provided for the respective photodiodes; an insulating film provided so as to cover the transistors; a first inorganic insulating film provided so as to cover the photodiodes; a first organic insulating film provided on the upper side of the first inorganic insulating film; and an upper conductive layer provided on the upper side of the first organic insulating film and electrically coupled to the photodiode. Each photodiode includes: first regions in each of which the p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer are directly in contact with one another; and a second region in which the p-type semiconductor layer and the i-type semiconductor layer are separate from each other. The adjacent first regions are coupled together by the p-type semiconductor layer.
    Type: Application
    Filed: August 17, 2023
    Publication date: December 7, 2023
    Inventors: Yoshitaka OZEKI, Takahiro TAKEUCHI
  • Publication number: 20230360884
    Abstract: A plasma processing apparatus includes: a chamber; first and second matching circuits; a first RF generator generating a first RF pulsed signal including a plurality of first pulse cycles in which each cycle includes first, second, and third periods, and the first RF pulsed signal has first, second, and third power levels in first, second, and third periods, respectively; a second RF generator generating a second RF pulsed signal including a plurality of second pulse cycles in which each cycle includes fourth and fifth periods, and the second RF pulsed signal has fourth and fifth power levels in fourth and fifth periods, respectively; and a third RF generator generating a third RF pulsed signal including a plurality of third pulse cycles in which each cycle includes sixth and seventh periods, and the third RF pulsed signal has sixth and seventh power levels in sixth and seventh periods, respectively.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 9, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Takahiro TAKEUCHI, Ken KOBAYASHI
  • Patent number: 11798787
    Abstract: A plasma processing apparatus includes: a source RF generator that generates a source RF pulsed signal of at least three power levels; first and second bias RF generators that generate first and second bias RF pulsed signals of at least two power levels; a synchronization signal generator that generates a synchronization signal; a first matching circuit connected to the source RF generator and an antenna, thereby allowing the source RF pulsed signal to be supplied from the source RF generator to the antenna through the first matching circuit; and a second matching circuit connected to the first and second bias RF generators and a substrate support, thereby allowing the first and second bias RF pulse signals to be supplied from the first and second bias RF generators to the substrate support through the second matching circuit.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: October 24, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Naoki Fujiwara, Mitsunori Ohata, Takahiro Takeuchi
  • Patent number: 11756767
    Abstract: A plasma processing apparatus includes: a chamber; first and second matching circuits; a first RF generator generating a first RF pulsed signal including a plurality of first pulse cycles in which each cycle includes first, second, and third periods, and the first RF pulsed signal has first, second, and third power levels in first, second, and third periods, respectively; a second RF generator generating a second RF pulsed signal including a plurality of second pulse cycles in which each cycle includes fourth and fifth periods, and the second RF pulsed signal has fourth and fifth power levels in fourth and fifth periods, respectively; and a third RF generator generating a third RF pulsed signal including a plurality of third pulse cycles in which each cycle includes sixth and seventh periods, and the third RF pulsed signal has sixth and seventh power levels in sixth and seventh periods, respectively.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: September 12, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takahiro Takeuchi, Ken Kobayashi
  • Publication number: 20220084789
    Abstract: A plasma processing apparatus includes: a chamber; first and second matching circuits; a first RF generator generating a first RF pulsed signal including a plurality of first pulse cycles in which each cycle includes first, second, and third periods, and the first RF pulsed signal has first, second, and third power levels in first, second, and third periods, respectively; a second RF generator generating a second RF pulsed signal including a plurality of second pulse cycles in which each cycle includes fourth and fifth periods, and the second RF pulsed signal has fourth and fifth power levels in fourth and fifth periods, respectively; and a third RF generator generating a third RF pulsed signal including a plurality of third pulse cycles in which each cycle includes sixth and seventh periods, and the third RF pulsed signal has sixth and seventh power levels in sixth and seventh periods, respectively.
    Type: Application
    Filed: September 15, 2021
    Publication date: March 17, 2022
    Applicant: Tokyo Electron Limited
    Inventors: Takahiro Takeuchi, Ken Kobayashi
  • Publication number: 20220084788
    Abstract: A plasma processing apparatus includes: a chamber; first and second matching circuits; a first RF generator that generates a first RF pulsed signal including pulse cycles in which each cycle includes first, second, and third periods, the first RF pulsed signal has first, second, and third power levels in the first, second, and third periods, respectively; a second RF generator that generates a second RF pulsed signal including the pulse cycles in which the second RF pulsed signal has fourth and fifth power levels in the first period and one of the second and third periods, respectively; and a third RF generator that generates a third RF pulsed signal including the pulse cycles in which the third RF pulsed signal has sixth and seventh power levels in the second period and one of the first and third periods, respectively.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 17, 2022
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Takahiro TAKEUCHI, Ken KOBAYASHI
  • Publication number: 20220068605
    Abstract: A plasma processing apparatus includes: a source RF generator that generates a source RF pulsed signal of at least three power levels; first and second bias RF generators that generate first and second bias RF pulsed signals of at least two power levels; a synchronization signal generator that generates a synchronization signal; a first matching circuit connected to the source RF generator and an antenna, thereby allowing the source RF pulsed signal to be supplied from the source RF generator to the antenna through the first matching circuit; and a second matching circuit connected to the first and second bias RF generators and a substrate support, thereby allowing the first and second bias RF pulse signals to be supplied from the first and second bias RF generators to the substrate support through the second matching circuit.
    Type: Application
    Filed: August 23, 2021
    Publication date: March 3, 2022
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Naoki FUJIWARA, Mitsunori OHATA, Takahiro TAKEUCHI
  • Patent number: 11187958
    Abstract: According to one embodiment, a display device includes a scanning line, a semiconductor layer, a first inorganic insulating film located between the scanning line and the semiconductor layer, a first signal line, a second inorganic insulating film having a main surface which contacts the first signal line and located between the semiconductor layer and the first signal line, a capacitance electrode contacting the main surface, a pixel electrode overlapping the capacitance electrode, and a third inorganic insulating film covering the first signal line and the capacitance electrode and located between the first signal line and the pixel electrode and between the capacitance electrode and the pixel electrode.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 30, 2021
    Assignee: Japan Display Inc.
    Inventors: Tomoyasu Hirano, Yoshitaka Ozeki, Koji Ishizaki, Takahiro Takeuchi, Koshiro Moriguchi
  • Patent number: 11150524
    Abstract: According to one embodiment, a display device includes a base substrate, a switching element including a semiconductor layer, a power supply line, a pixel electrode electrically connected to the switching element, a capacitance electrode positioned between the base substrate and the pixel electrode and electrically connected to the power supply line, a first interlayer insulating film positioned between the pixel electrode and the capacitance electrode, a common electrode, and an electrophoretic element positioned between the pixel electrode and the common electrode. An edge of the capacitance electrode overlaps the pixel electrode over the entire periphery thereof.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: October 19, 2021
    Assignee: Japan Display Inc.
    Inventors: Yoshitaka Ozeki, Tadayoshi Katsuta, Koji Ishizaki, Takahiro Takeuchi, Koshiro Moriguchi
  • Publication number: 20210026215
    Abstract: According to one embodiment, a display device includes a first conductive layer, a second conductive layer overlapping the first conductive layer, a first capacitive portion located in a same layer as the first conductive layer, a second capacitive portion located in a same layer as the second conductive layer and overlapping the first capacitive portion, a first inorganic insulating film located between the first conductive layer and the second conductive layer and between the first capacitive portion and the second capacitive portion, a drain electrode electrically connected to the second capacitive portion, a pixel electrode electrically connected to the drain electrode.
    Type: Application
    Filed: October 15, 2020
    Publication date: January 28, 2021
    Applicant: Japan Display Inc.
    Inventors: Koji ISHIZAKI, Yoshitaka OZEKI, Takahiro TAKEUCHI, Koshiro MORIGUCHI, Tomoyasu HIRANO
  • Patent number: 10903243
    Abstract: According to one embodiment, there is provided a display device including a basement, a first switching element which is provided on the basement and includes a first semiconductor layer and a first gate electrode, a second switching element which is provided on the basement and includes a second semiconductor layer and a second gate electrode, and a pixel electrode which is electrically connected to the first switching element. A distance between the first semiconductor layer and the first gate electrode is greater than a distance between the second semiconductor layer and the second gate electrode.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: January 26, 2021
    Assignee: Japan Display Inc.
    Inventors: Yoshitaka Ozeki, Nobutaka Ozaki, Koshiro Moriguchi, Takahiro Takeuchi, Koji Ishizaki
  • Patent number: 10871698
    Abstract: According to one embodiment, a display device includes a capacitance electrode, a first pixel electrode overlapping the capacitance electrode, a second pixel electrode overlapping the capacitance electrode, a shield layer disposed between the first pixel electrode and the second pixel electrode, a common electrode, and an electrophoretic element disposed between the common electrode and the first pixel electrode and between the common electrode and the shield layer. The first pixel electrode and the second pixel electrode are arranged along a first direction, and the shield layer extends in a second direction which crosses the first direction between the first pixel electrode and the second pixel electrode.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: December 22, 2020
    Assignee: Japan Display Inc.
    Inventors: Takahiro Takeuchi, Yoshitaka Ozeki, Koji Ishizaki, Tomoyasu Hirano, Koshiro Moriguchi
  • Patent number: 10866474
    Abstract: According to one embodiment, a display device includes a switching element, an organic insulating film which covers the switching element, a reflective film in contact with the organic insulating film, a first transparent conductive film which covers the reflective film, a first capacitance insulating film which covers the first transparent conductive film, a pixel electrode disposed on the first capacitance insulating film and electrically connected to the switching element, an electrophoretic element disposed on the pixel electrode and a common electrode disposed on the electrophoretic element.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 15, 2020
    Assignee: Japan Display Inc.
    Inventors: Yoshitaka Ozeki, Koji Ishizaki, Takahiro Takeuchi, Koshiro Moriguchi
  • Patent number: 10824041
    Abstract: According to one embodiment, a display device includes a switching element including a source electrode and a drain electrode, an inorganic insulating film in contact with the source electrode and the drain electrode, a metal film in contact with the inorganic insulating film and including an opening in a position superimposed on the drain electrode, a capacitor insulating film covering the metal film, an pixel electrode located on the capacitor insulating film and electrically connected to the drain electrode, an electrophoretic element located on the pixel electrode and a common electrode located on the electrophoretic element, and the metal film includes a forward tapered end portion in the opening.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: November 3, 2020
    Assignee: Japan Display Inc.
    Inventors: Yoshitaka Ozeki, Koji Ishizaki, Takahiro Takeuchi, Koshiro Moriguchi
  • Publication number: 20190361314
    Abstract: According to one embodiment, a display device includes a scanning line, a semiconductor layer, a first inorganic insulating film located between the scanning line and the semiconductor layer, a first signal line, a second inorganic insulating film having a main surface which contacts the first signal line and located between the semiconductor layer and the first signal line, a capacitance electrode contacting the main surface, a pixel electrode overlapping the capacitance electrode, and a third inorganic insulating film covering the first signal line and the capacitance electrode and located between the first signal line and the pixel electrode and between the capacitance electrode and the pixel electrode.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 28, 2019
    Applicant: Japan Display Inc.
    Inventors: Tomoyasu HIRANO, Yoshitaka OZEKI, Koji ISHIZAKI, Takahiro TAKEUCHI, Koshiro MORIGUCHI