Abstract: There are provided a logic simulator apparatus and a circuit simulation apparatus capable of simulation based on signal propagation delay time with high reliability. A voltage drop calculating portion (9) calculates a voltage drop value (Vi) on the basis of power-supply information (D4), drain current (Ii) and voltage drop resistance (Ri). A propagation delay calculating portion (10) calculates delay time (Di) required for each element to propagate a logic signal value on the basis of gain coefficient (.beta.i), interconnection parasitic capacitance (Cj) and voltage drop value (Vi). A logic simulation performing portion (12) performs the logic simulation on the basis of the circuit connection data (D22) provided with the delay time (Di). Accordingly, logic and circuit simulation can be accomplished on the basis of the signal propagation delay time with high reliability.

Abstract: A timing simulation system has a layout pattern data storage portion, a data extracting portion, a process parameter storage portion, a gain coefficient calculating portion, an attendant capacitance supply portion, and a timing simulation executing portion. The gain coefficient calculating portion and the attendant capacitance calculating portion calculate gain coefficients and attendant capacitances peculiar to elements and wires from the circuit connection data extracted from layout pattern data of a logic circuit, and the gain coefficient supply portion and the attendant capacitance supply portion set the gain coefficients and the attendant capacitances.

Abstract: A MOST output signal determiner (4) with output signal strength verifying function receives a circuit connection data (D4) with MOS input information to determine the signal strength of an output signal which appears at an output terminal (drain or source) of an MOS transistor as a function of an input signal. A logic simulator verifies circuit operating characteristics in consideration for signal transmitting characteristics on the input signal of the MOST, the presence/absence of a through current in the MOST and an accurate state transition delay time through the MOST.

Abstract: In the inventive layout pattern verification system, verification data employed by a verification data judging part for judging effectiveness/defectiveness of the electrical property of a logic circuit formed by a layout pattern are data calculated by a verification data calculation part on the basis of reference circuit constants extracted from layout pattern data by a second data extraction part and process parameters supplied by a process parameter supply part, i.e., data obtained with no circuit simulation. Thus, the electrical property of the layout pattern of a large-scale logic circuit can also be easily verified by judging effectiveness/defectiveness of the electrical property of the logic circuit formed by a layout pattern through a verification data judging part on the basis of the verification data.