Abstract: A microprocessor to which a coprocessor can be connected includes a first terminal to be connected to the coprocessor to receive an operation request signal therefrom and a second terminal to be connected to the coprocessor to supply an operation-acknowledge signal thereto. A detection circuit detects an instruction to be executed by the coprocessor and produces a detection signal. A monitor circuit, responsive to the detection signal, monitors a level of the first terminal to produce an acknowledge signal when the first terminal is at an active level and an interrupt signal when the first terminal is at an inactive level. A circuit responsive to the acknowledge signal outputs the operation-acknowledge signal to the second terminal and a circuit responsive to the interrupt signal generates an interruption request signal to bring the microprocessor into an interruption operation. The microprocessor thereby performs the interruption operation in the absence of the coprocessor.

Abstract: A microprocessor includes an execution unit executing a program according to an instruction, an instruction prefetch circuit storing a plurality of instructions to be executed by the execution unit, a refresh control circuit controlling a refresh operation of a dynamic memory coupled to an external bus and a control unit. The control unit receives bus access request signals from the execution unit and from the instruction prefetch circuit, respectively, and a refresh request signal from the refresh control circuit and sends a refresh grant signal to the refresh control circuit in response to the refresh request signal when both the bus access request signals are absent. The refresh control circuit generates a first refresh request signal and a second refresh request signal.

Abstract: A microprocessor includes an execution unit executing a program according to an instruction, an instruction prefetch circuit storing a plurality of instructions to be executed by the execution unit, a refresh control circuit controlling a refresh operation of a dynamic memory coupled to an external bus and a control unit. The control unit receives bus access request signals from the execution unit and from the instruction prefetch circuit, respectively, and a refresh request signal from the refresh control circuit and sends a refresh grant signal to the refresh control circuit in response to the refresh request signal when both the bus access request signals are absent. Thus, the refresh operation can be performed without exerting a harmful influence on the operations of the execution unit and the instruction prefetch circuit. The refresh control circuit may generate a first refresh request signal and a second refresh request signal.