Abstract: The present invention addresses the problem of providing a soybean-derived raw material-containing food or beverage that improves problems with flavor and physical properties, such as the grassy smell caused by soybean raw materials, and markedly improves product quality, in a soybean-derived raw material-containing food or beverage using conventional soybean raw materials such soymilk or tofu. Provided are a milk-substitute composition, and an egg-yolk substitute composition, etc., characterized by including a soybean emulsion composition having a protein content relative to dry material of at least 25 wt %, a fat content (as a chloroform/methanol mixed solvent extract) relative to the protein content of at least 100 wt %, and an LCI value of at least 55%. Also provided are a variety of soybean-derived raw material-containing food and beverages using these compositions.

Abstract: The present invention addresses the problem of providing a soybean-derived raw material-containing food or beverage that improves problems with flavor and physical properties, such as the grassy smell caused by soybean raw materials, and markedly improves product quality, in a soybean-derived raw material-containing food or beverage using conventional soybean raw materials such soymilk or tofu. Provided are a milk-substitute composition, and an egg-yolk substitute composition, etc., characterized by including a soybean emulsion composition having a protein content relative to dry material of at least 25 wt %, a fat content (as a chloroform/methanol mixed solvent extract) relative to the protein content of at least 100 wt %, and an LCI value of at least 55%. Also provided are a variety of soybean-derived raw material-containing food and beverages using these compositions.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A semiconductor device includes an SOI substrate, trench memory cells including trench capacitors formed in the SOI substrate and a mesa or trench isolation region for isolating the trench memory cells. As a result, the trench memory cells are isolated more completely and soft errors are reduced.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A semiconductor device includes an SOI substrate, trench memory cells including trench capacitors formed in the SOI substrate and a mesa or trench isolation region for isolating the trench memory cells. As a result, the trench memory cells are isolated more completely and soft errors are reduced.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: A program data latch circuit supplies one of a write bit line potential and a write prohibiting potential corresponding to multilevel data to be written, to a bit line in accordance with a level of a write control signal in a write operation. On the other hand, a program sense latch circuit compares a threshold value of a memory cell transistor sensed through the bit line with a reference potential, changes the level of the write control signal if the threshold value becomes a value corresponding to the multilevel data and instructs output of the write prohibiting potential in a verification operation.

Abstract: A semiconductor device includes an SOI substrate, trench memory cells including trench capacitors formed in the SOI substrate and a mesa or trench isolation region for isolating the trench memory cells. As a result, the trench memory cells are isolated more completely and soft errors are reduced.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

Abstract: The present invention provides a non-volatile semiconductor memory device including a sector selecting circuit. When a non-defective sector is designated by an address signal, a spare decoder outputs a signal such that a NAND gate can select the non-defective sector, when a defective sector is designated by the address signal, the spare decoder outputs a signal for activating an alternate non-defective sector, and when the alternate non-defective sector is designated by the address signal, a signal for making all of a plurality of sectors non-selective. As a result, it is possible to reduce a defective rate of the non-volatile semiconductor memory device.

Abstract: A program data latch circuit supplies one of a write bit line potential and a write prohibiting potential corresponding to multilevel data to be written, to a bit line in accordance with a level of a write control signal in a write operation. On the other hand, a program sense latch circuit compares a threshold value of a memory cell transistor sensed through the bit line with a reference potential, changes the level of the write control signal if the threshold value becomes a value corresponding to the multilevel data and instructs output of the write prohibiting potential in a verification operation.

Abstract: In the data writing sequence, judgement of writing is divided into two stages of judgement 1 and judgement 2. In the judgement 1, it is determined whether the data writing has been completed for at least one of a plurality of memory cells, and in the judgement 2, it is determined whether the data writing has been completed for all the memory cells. Changing the writing conditions for the judgements 1 and 2 enables judgement of the data writing in an early stage.

Abstract: In the data writing sequence, judgement of writing is divided into two stages of judgement 1 and judgement 2. In the judgement 1, it is determined whether the data writing has been completed for at least one of a plurality of memory cells, and in the judgement 2, it is determined whether the data writing has been completed for all the memory cells. Changing the writing conditions for the judgements 1 and 2 enables judgement of the data writing in an early stage.

Abstract: A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.