Patents by Inventor Takahiro Tsurudo
Takahiro Tsurudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230307434Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.Type: ApplicationFiled: May 31, 2023Publication date: September 28, 2023Applicant: Kioxia CorporationInventors: Hiroshi MAEJIMA, Katsuaki ISOBE, Nobuaki OKADA, Hiroshi NAKAMURA, Takahiro TSURUDO
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Patent number: 11705443Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.Type: GrantFiled: September 4, 2020Date of Patent: July 18, 2023Assignee: Kioxia CorporationInventors: Hiroshi Maejima, Katsuaki Isobe, Nobuaki Okada, Hiroshi Nakamura, Takahiro Tsurudo
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Patent number: 11626394Abstract: A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.Type: GrantFiled: February 25, 2021Date of Patent: April 11, 2023Assignee: KIOXIA CORPORATIONInventors: Akihiko Chiba, Takahiro Tsurudo, Kenichi Matoba, Yoshifumi Shimamura, Hiroaki Nakasa, Hiroyuki Takenaka
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Publication number: 20230083158Abstract: A semiconductor device includes an active region, and an edge seal formed on at least a portion of an outer edge of the active region. The edge seal includes a first stacked body having a first conductive layer, and a second stacked body having a second conductive layer. The first conductive layer is coupled to a first voltage, the second conductive layer is coupled to a second voltage different from the first voltage, and the first conductive layer faces the second conductive layer.Type: ApplicationFiled: February 28, 2022Publication date: March 16, 2023Applicant: Kioxia CorporationInventors: Kenichi MATOBA, Takahiro TSURUDO, Yoshiaki TAKAHASHI, Yoichi MIZUTA, Yoshifumi SHIMAMURA, Toru OZAWA, Takumi KOSAKI, Kouji NAKAO
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Publication number: 20220285284Abstract: According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns that are disposed in a repeating manner in at least one direction. The semiconductor device includes a discrimination pattern provided in the circuit pattern and configured to discriminate the unit patterns from each other.Type: ApplicationFiled: August 25, 2021Publication date: September 8, 2022Applicant: Kioxia CorporationInventors: Yoichi MIZUTA, Takahiro TSURUDO, Yoshiaki TAKAHASHI, Kenichi MATOBA, Yoshifumi SHIMAMURA, Toru OZAWA, Takumi KOSAKI, Kouji NAKAO
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Publication number: 20220077128Abstract: A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.Type: ApplicationFiled: February 25, 2021Publication date: March 10, 2022Applicant: Kioxia CorporationInventors: Akihiko CHIBA, Takahiro TSURUDO, Kenichi MATOBA, Yoshifumi SHIMAMURA, Hiroaki NAKASA, Hiroyuki TAKENAKA
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Publication number: 20210118862Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.Type: ApplicationFiled: September 4, 2020Publication date: April 22, 2021Applicant: Kioxia CorporationInventors: Hiroshi MAEJIMA, Katsuaki ISOBE, Nobuaki OKADA, Hiroshi NAKAMURA, Takahiro TSURUDO
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Patent number: 10861865Abstract: A semiconductor storage device includes first high-potential wirings, second high-potential wirings, a first low-potential wiring, a second low-potential wiring, a first branch wiring, and a second branch wiring formed in a wiring layer between a memory cell array and a semiconductor substrate and each extending in a first direction. The first branch wiring is electrically connected to the first low-potential wiring, and is adjacent to the first low-potential wiring on one side in a second direction perpendicular to the first direction of the first low-potential wiring. The second branch wiring is electrically connected to the second low-potential wiring, and is adjacent to the second low-potential wiring on the other side in the second direction of the second low-potential wiring. A first via is provided to contact the first branch wiring, and a second via is provided to contact the second branch wiring.Type: GrantFiled: September 5, 2019Date of Patent: December 8, 2020Assignee: Toshiba Memory CorporationInventors: Yoshiaki Takahashi, Takahiro Tsurudo, Kiyofumi Sakurai
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Publication number: 20200295024Abstract: A semiconductor storage device includes first high-potential wirings, second high-potential wirings, a first low-potential wiring, a second low-potential wiring, a first branch wiring, and a second branch wiring formed in a wiring layer between a memory cell array and a semiconductor substrate and each extending in a first direction. The first branch wiring is electrically connected to the first low-potential wiring, and is adjacent to the first low-potential wiring on one side in a second direction perpendicular to the first direction of the first low-potential wiring. The second branch wiring is electrically connected to the second low-potential wiring, and is adjacent to the second low-potential wiring on the other side in the second direction of the second low-potential wiring. A first via is provided to contact the first branch wiring, and a second via is provided to contact the second branch wiring.Type: ApplicationFiled: September 5, 2019Publication date: September 17, 2020Applicant: Toshiba Memory CorporationInventors: Yoshiaki TAKAHASHI, Takahiro TSURUDO, Kiyofumi SAKURAI
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Publication number: 20130075934Abstract: In one embodiment, a semiconductor device includes a first wiring provided in a first wiring layer along a first direction, a second wiring provided in a second wiring layer along a second direction orthogonal to the first direction, the second wiring intersecting with the first wiring at a first intersect portion, and a third wiring provided close to and along the second wiring in the second wiring layer, the third wiring intersecting with the first wiring at a second intersect portion, wherein a distance between the second wiring in the first intersection portion and the third wiring in the second intersection portion is narrower than a distance between the second wiring another than the first intersection portion and the third wiring another than the second intersection portion.Type: ApplicationFiled: March 16, 2012Publication date: March 28, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Osamu Oto, Takahiro Tsurudo, Kenichi Matoba, Jumpei Sato