Abstract: A semiconductor memory device includes a memory cell array, an address register for taking in an address synchronizing with a clock, a decode circuit for selecting a memory cell of the memory cell array by decoding the address retained in the address register, a reading/writing circuit for reading data from the memory cell array and writing the data to the memory cell array, a data register for temporarily retaining the data read from and written to the memory cell array, synchronizing with the clock, and an echo signal generation circuit, synchronizing with the clock, for outputting an echo signal composed of a predetermined expected value pattern for notifying the outside of a data output with a delay time equal to a transmission delay time of the output data read from the memory cell array.

Abstract: A semiconductor memory device includes a memory cell array, an address register for taking in an address synchronizing with a clock, a decode circuit for selecting a memory cell of the memory cell array by decoding the address retained in the address register, a reading/writing circuit for reading data from the memory cell array and writing the data to the memory cell array, a data register for temporarily retaining the data read from and written to the memory cell array, synchronizing with the clock, and an echo signal generation circuit, synchronizing with the clock, for outputting an echo signal composed of a predetermined expected value pattern for notifying the outside of a data output with a delay time equal to a transmission delay time of the output data read from the memory cell array.

Abstract: A semiconductor memory device is disclosed which can read a plurality of bit units and which can suppress an increase in current consumption and in chip size even if the number of bits serving as a unit of reading is increased. The semiconductor memory device includes a memory cell array having memory cells arranged in a matrix form such that a plurality of columns are divided into a plurality of sections, a plurality of column selection circuits for selecting each of the columns of the memory cell array, a sense amplifier for sense-amplifying data transferred through the data lines, and a column selection control circuit for controlling the plurality of column selection circuits to select one of the plurality of sections of the memory cell array and one of the columns of the sections and to read bit data from the selected column, sequentially.