Patents by Inventor Takahiro Tuji

Takahiro Tuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8587286
    Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: November 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada
  • Publication number: 20130280857
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Application
    Filed: June 13, 2013
    Publication date: October 24, 2013
    Inventors: Masashi TSUBUKU, Shuhei YOSHITOMI, Takahiro TUJI, Miyuki HOSOBA, Junichiro SAKATA, Hiroyuki TOMATSU, Masahiko HAYAKAWA
  • Patent number: 8466014
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: June 18, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Shuhei Yoshitomi, Takahiro Tuji, Miyuki Hosoba, Junichiro Sakata, Hiroyuki Tomatsu, Masahiko Hayakawa
  • Patent number: 8456148
    Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: June 4, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada
  • Patent number: 8368209
    Abstract: The problem of damage on an antenna or a circuit (electrostatic breakdown) due to discharge of electric charge accumulated in an insulator is solved; and the problem of NAKANUKE failure is solved. A pair of conductive layers, a pair of insulators provided between the pair of conductive layers, and a chip which is provided between the pair of insulators and includes an antenna, an analog circuit, and a digital circuit are provided, in which an opening is provided for at least one of the pair of conductive layers, and the opening is provided at a position which overlaps at least the analog circuit.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiro Tuji, Koichiro Kamata
  • Patent number: 8344719
    Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada
  • Publication number: 20120289008
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Application
    Filed: July 26, 2012
    Publication date: November 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masashi TSUBUKU, Shuhei YOSHITOMI, Takahiro TUJI, Miyuki HOSOBA, Junichiro SAKATA, Hiroyuki TOMATSU, Masahiko HAYAKAWA
  • Patent number: 8236627
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Shuhei Yoshitomi, Takahiro Tuji, Miyuki Hosoba, Junichiro Sakata, Hiroyuki Tomatsu, Masahiko Hayakawa
  • Publication number: 20110063803
    Abstract: The problem of damage on an antenna or a circuit (electrostatic breakdown) due to discharge of electric charge accumulated in an insulator is solved; and the problem of NAKANUKE failure is solved. A pair of conductive layers, a pair of insulators provided between the pair of conductive layers, and a chip which is provided between the pair of insulators and includes an antenna, an analog circuit, and a digital circuit are provided, in which an opening is provided for at least one of the pair of conductive layers, and the opening is provided at a position which overlaps at least the analog circuit.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 17, 2011
    Inventors: Takahiro TUJI, Koichiro KAMATA
  • Publication number: 20110059575
    Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.
    Type: Application
    Filed: August 30, 2010
    Publication date: March 10, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masashi TSUBUKU, Shuhei YOSHITOMI, Takahiro TUJI, Miyuki HOSOBA, Junichiro SAKATA, Hiroyuki TOMATSU, Masahiko HAYAKAWA
  • Publication number: 20100181985
    Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
    Type: Application
    Filed: January 13, 2010
    Publication date: July 22, 2010
    Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada