Patents by Inventor Takahiro Tuji
Takahiro Tuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8587286Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.Type: GrantFiled: January 13, 2010Date of Patent: November 19, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada
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Publication number: 20130280857Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.Type: ApplicationFiled: June 13, 2013Publication date: October 24, 2013Inventors: Masashi TSUBUKU, Shuhei YOSHITOMI, Takahiro TUJI, Miyuki HOSOBA, Junichiro SAKATA, Hiroyuki TOMATSU, Masahiko HAYAKAWA
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Patent number: 8466014Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.Type: GrantFiled: July 26, 2012Date of Patent: June 18, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masashi Tsubuku, Shuhei Yoshitomi, Takahiro Tuji, Miyuki Hosoba, Junichiro Sakata, Hiroyuki Tomatsu, Masahiko Hayakawa
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Patent number: 8456148Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.Type: GrantFiled: January 13, 2010Date of Patent: June 4, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada
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Patent number: 8368209Abstract: The problem of damage on an antenna or a circuit (electrostatic breakdown) due to discharge of electric charge accumulated in an insulator is solved; and the problem of NAKANUKE failure is solved. A pair of conductive layers, a pair of insulators provided between the pair of conductive layers, and a chip which is provided between the pair of insulators and includes an antenna, an analog circuit, and a digital circuit are provided, in which an opening is provided for at least one of the pair of conductive layers, and the opening is provided at a position which overlaps at least the analog circuit.Type: GrantFiled: September 16, 2010Date of Patent: February 5, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takahiro Tuji, Koichiro Kamata
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Patent number: 8344719Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.Type: GrantFiled: January 13, 2010Date of Patent: January 1, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada
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Publication number: 20120289008Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.Type: ApplicationFiled: July 26, 2012Publication date: November 15, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Masashi TSUBUKU, Shuhei YOSHITOMI, Takahiro TUJI, Miyuki HOSOBA, Junichiro SAKATA, Hiroyuki TOMATSU, Masahiko HAYAKAWA
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Patent number: 8236627Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.Type: GrantFiled: August 30, 2010Date of Patent: August 7, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masashi Tsubuku, Shuhei Yoshitomi, Takahiro Tuji, Miyuki Hosoba, Junichiro Sakata, Hiroyuki Tomatsu, Masahiko Hayakawa
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Publication number: 20110063803Abstract: The problem of damage on an antenna or a circuit (electrostatic breakdown) due to discharge of electric charge accumulated in an insulator is solved; and the problem of NAKANUKE failure is solved. A pair of conductive layers, a pair of insulators provided between the pair of conductive layers, and a chip which is provided between the pair of insulators and includes an antenna, an analog circuit, and a digital circuit are provided, in which an opening is provided for at least one of the pair of conductive layers, and the opening is provided at a position which overlaps at least the analog circuit.Type: ApplicationFiled: September 16, 2010Publication date: March 17, 2011Inventors: Takahiro TUJI, Koichiro KAMATA
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Publication number: 20110059575Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.Type: ApplicationFiled: August 30, 2010Publication date: March 10, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Masashi TSUBUKU, Shuhei YOSHITOMI, Takahiro TUJI, Miyuki HOSOBA, Junichiro SAKATA, Hiroyuki TOMATSU, Masahiko HAYAKAWA
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Publication number: 20100181985Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.Type: ApplicationFiled: January 13, 2010Publication date: July 22, 2010Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada