Patents by Inventor Takahiro UMEZAKI

Takahiro UMEZAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136206
    Abstract: A substrate processing apparatus that dries a liquid adhering to a substrate by using a processing fluid in a supercritical state, includes: a processing container in which the substrate is accommodated; a plurality of pipes configured to allow the processing fluid to flow to and from the processing container therethrough; a first fluid heating device configured to heat a first pipe that supplies the processing fluid to an interior of the processing container among the plurality of pipes; and a second fluid heating device configured to heat a second pipe that discharges the processing fluid from the interior of the processing container among the plurality of pipes.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 25, 2024
    Inventors: Takahiro HAYASHIDA, Shigeru MORIYAMA, Shota UMEZAKI
  • Patent number: 11707756
    Abstract: A coating system includes coating robots configured to coat a vehicle, and an operation robot. The operation robot includes a first arm configured to turn around a first axis; a second arm configured to turn around a second axis parallel to the first axis; a third arm configured to turn around a third axis parallel to the first axis; a fourth arm configured to turn around a fourth axis perpendicular to the first axis; a fifth arm configured to turn around a fifth axis parallel to the fourth axis; and a tip jig is supported at the fifth arm and is configured to turn around a sixth axis. The sixth axis is selectively parallel to the fifth axis or perpendicular to a plane which includes the fourth axis and the fifth axis.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: July 25, 2023
    Assignee: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Katsuhiko Yoshino, Satoshi Sueyoshi, Takahiro Umezaki, Tsuyoshi Ito
  • Publication number: 20210146393
    Abstract: A coating system includes coating robots configured to coat a vehicle, and an operation robot. The operation robot includes a first arm configured to turn around a first axis; a second arm configured to turn around a second axis parallel to the first axis; a third arm configured to turn around a third axis parallel to the first axis; a fourth arm configured to turn around a fourth axis perpendicular to the first axis; a fifth arm configured to turn around a fifth axis parallel to the fourth axis; and a tip jig is supported at the fifth arm and is configured to turn around a sixth axis. The sixth axis is selectively parallel to the fifth axis or perpendicular to a plane which includes the fourth axis and the fifth axis.
    Type: Application
    Filed: January 7, 2021
    Publication date: May 20, 2021
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Katsuhiko YOSHINO, Satoshi SUEYOSHI, Takahiro UMEZAKI, Tsuyoshi ITO
  • Publication number: 20180221904
    Abstract: A coating system includes: a plurality of coating robots fixed in a coating booth, the plurality of coating robots being configured to coat a vehicle conveyed in a predetermined conveyance direction; and a fixed-type operation robot fixed in the coating booth on an upstream side or a downstream side of the plurality of coating robots in the conveyance direction, the fixed-type operation robot being configured to operate an open/close member provided at a front or a rear portion of the vehicle, the fixed-type operation robot including a first arm turning around a vertical axis.
    Type: Application
    Filed: February 5, 2018
    Publication date: August 9, 2018
    Applicant: KABUSHIKI KAISHA YASKAWA DENKI
    Inventors: Katsuhiko YOSHINO, Satoshi SUEYOSHI, Takahiro UMEZAKI, Tsuyoshi ITO
  • Publication number: 20150326238
    Abstract: A microcomputer includes a bus, a CPU (Central Processing Unit) coupled to the bus, a RAM (Random-access Memory) coupled to the bus, and an AD (Analog-to-Digital) converter coupled to the bus. The AD converter includes a switching circuit for switching between an analog signal and a reference potential, a first DA (Digital-to-Analog) converter including a plurality of first capacitors each having one end that can be individually coupled to the switching circuit and the other end coupled to a common output line, one or a plurality of testing capacitors that are dedicated for testing, each having one end to which the reference potential or a potential obtained by dividing the reference potential can be individually inputted, and a control circuit. In a normal mode, the control circuit determines a digital value corresponding to the analog signal, based on the output line.
    Type: Application
    Filed: July 17, 2015
    Publication date: November 12, 2015
    Inventors: Takahiro UMEZAKI, Yasutaka HORIKOSHI, Takehiro MIKAMI
  • Patent number: 9124288
    Abstract: To determine the accuracy of an AD converter more simply than in the related art, a semiconductor device includes a successive approximation AD converter. The AD converter includes one or a plurality of testing capacitors used in a test mode, separately from a C-DAC used for AD conversion in a normal mode. In the test mode, the accuracy of a capacitor under test among a plurality of capacitors configuring the C-DAC is determined by comparing a potential occurring in the capacitor under test and a potential occurring in the testing capacitors.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: September 1, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiro Umezaki, Yasutaka Horikoshi, Takehiro Mikami
  • Publication number: 20150188557
    Abstract: To determine the accuracy of an AD converter more simply than in the related art, a semiconductor device includes a successive approximation AD converter. The AD converter includes one or a plurality of testing capacitors used in a test mode, separately from a C-DAC used for AD conversion in a normal mode. In the test mode, the accuracy of a capacitor under test among a plurality of capacitors configuring the C-DAC is determined by comparing a potential occurring in the capacitor under test and a potential occurring in the testing capacitors.
    Type: Application
    Filed: December 19, 2014
    Publication date: July 2, 2015
    Inventors: Takahiro UMEZAKI, Yasutaka Horikoshi, Takehiro Mikami
  • Publication number: 20130025399
    Abstract: A robot according to an aspect of an embodiment includes: an articulated arm; and a speed reducer that is provided in a joint of the articulated arm. The articulated arm performs a multi-axis operation. The speed reducer has rigidity for which an acquisition value obtained by acquiring a deflection amount of a predetermined representative position at the articulated arm for each dimension of a three-dimensional coordinate system is not more than a threshold corresponding to a target precision of the articulated arm.
    Type: Application
    Filed: February 8, 2012
    Publication date: January 31, 2013
    Applicant: KABISHIKI KAISHA YASKAWA DENKI
    Inventors: Kaori SAKAKI, Takahiro UMEZAKI, Atsushi ICHIBANGASE