Patents by Inventor Takahiro Yurino

Takahiro Yurino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8940583
    Abstract: In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takahiro Yurino
  • Patent number: 8791555
    Abstract: A semiconductor device including a semiconductor element, a die pad of a plane size smaller than that of the semiconductor element, a plurality of hanging leads extending from the die pad, and sealing resin for covering the semiconductor element, the die pad, and the hanging leads. The width of a first main surface of each hanging lead, integrated with the mounting surface of the die pad, is smaller than the width of a second main surface thereof, integrated with the opposite surface of the die pad.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takahiro Yurino
  • Patent number: 8664046
    Abstract: In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 4, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Takahiro Yurino
  • Patent number: 8610253
    Abstract: A lead frame includes a die stage; an inner lead provided near the die stage; and a bus bar provided between the die stage and the inner lead and supported by a hanging lead, wherein the hanging lead is inclined with respect to the inner lead, and a wire connection face of the bus bar is displaced with respect to a wire connection face of the inner lead in a direction of a frame thickness.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: December 17, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takahiro Yurino, Hiroshi Aoki, Tatsuya Takaku
  • Publication number: 20120074550
    Abstract: A lead frame includes a die stage; an inner lead provided near the die stage; and a bus bar provided between the die stage and the inner lead and supported by a hanging lead, wherein the hanging lead is inclined with respect to the inner lead, and a wire connection face of the bus bar is displaced with respect to a wire connection face of the inner lead in a direction of a frame thickness.
    Type: Application
    Filed: June 27, 2011
    Publication date: March 29, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Takahiro Yurino, Hiroshi Aoki, Tatsuya Takaku
  • Publication number: 20110278708
    Abstract: A lead frame includes a die stage on which a semiconductor element is mounted, a plurality of connection terminals radially arranged around the die stage, and a plurality of wire connection portions which are each provided at a leading end portion on the die stage side of one of the plurality of connection terminals. Moreover, a fixing tape is attached to back surface sides of the wire connection portions and fixes the plurality of wire connection portions all together. Adjacent two of the wire connection portions are staggered in a longitudinal direction of the corresponding connection terminals, and a portion of the connection terminal running along the wire connection portion of the adjacent connection terminal is formed to be narrower and thinner than the wire connection portion.
    Type: Application
    Filed: February 24, 2011
    Publication date: November 17, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Takahiro Yurino
  • Publication number: 20110233738
    Abstract: A semiconductor device including a semiconductor element, a die pad of a plane size smaller than that of the semiconductor element, a plurality of hanging leads extending from the die pad, and sealing resin for covering the semiconductor element, the die pad, and the hanging leads. The width of a first main surface of each hanging lead, integrated with the mounting surface of the die pad, is smaller than the width of a second main surface thereof, integrated with the opposite surface of the die pad.
    Type: Application
    Filed: February 11, 2011
    Publication date: September 29, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Takahiro Yurino
  • Publication number: 20100310781
    Abstract: In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals.
    Type: Application
    Filed: August 16, 2010
    Publication date: December 9, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Takahiro Yurino
  • Publication number: 20080290483
    Abstract: A structure of a semiconductor device is provided, where intervals can be narrowed between leads arranged around a semiconductor element to increase the number of leads, and electrical interference is prevented or reduced between the leads to cause no crosstalk between the leads. The semiconductor device of the present invention includes a semiconductor element and a plurality of leads arranged around the semiconductor element. The plurality of leads include a plurality of first leads and a plurality of second leads. The plurality of first leads are connected to electrode terminals of the semiconductor element through connection members. The plurality of second leads are arranged between the first leads and are not connected to the electrode terminals of the semiconductor element.
    Type: Application
    Filed: April 30, 2008
    Publication date: November 27, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Takahiro YURINO
  • Publication number: 20030227073
    Abstract: In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals.
    Type: Application
    Filed: January 6, 2003
    Publication date: December 11, 2003
    Applicant: Fujitsu Limited
    Inventor: Takahiro Yurino
  • Patent number: 6232147
    Abstract: A semiconductor device equipped with secondary pads having adequate arrangement for an arbitrary packaging process. The secondary pads are connected with the primary pads of the semiconductor device with a novel lead wire structure, which is characterized by its low electric resistance, good mechanical strength to protect active components of the device, good adhesion to bumps, and anti-electromigration property.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: May 15, 2001
    Assignee: Fujitsu Limited
    Inventors: Hirohisa Matsuki, Kenichi Kado, Eiji Watanabe, Kazuyuki Imamura, Takahiro Yurino
  • Patent number: 5969424
    Abstract: A semiconductor device equipped with secondary pads having adequate arrangement for an arbitrary packaging process. The secondary pads are connected with the primary pads of the semiconductor device with a novel lead wire structure, which is characterized by its low electric resistance, good mechanical strength to protect active components of the device, good adhesion to bumps, and anti-electromigration property.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: October 19, 1999
    Assignee: Fujitsu Limited
    Inventors: Hirohisa Matsuki, Kenichi Kado, Eiji Watanabe, Kazuyuki Imamura, Takahiro Yurino