Abstract: In a peripheral circuit region requiring a conductive path between layers at the periphery of a memory cell array region, a conductive path is provided, after removing a silicon nitride film used for self-alignment contact from the area of the contacting portion of a conductor, by forming an interlayer oxide film on the conductor and providing an opening through the interlayer oxide film. Alternatively, a conductive path is provided, after forming the interlayer oxide film on the silicon nitride film used for self-alignment contact, by forming an opening throughout the interlayer oxide film and silicon nitride film.

Abstract: A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. n-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions.

Abstract: In a dynamic semiconductor memory device including a thin film SOI/MOSFET having a semiconductor layer on an insulator as an active region, an "L" level potential of a memory cell transistor, which connects/disconnects a capacitor for storing data as electric charges and a bit line for reading/writing data, is set at a fixed value higher than a ground potential and lower than a power supply potential, and a substrate bias is set at the ground potential. Even if isolation is carried out by LOCOS, sub-threshold leakage current due to a parasitic MOS in the vicinity of LOCOS edge can be suppressed because the potential of a word line is lower than that of the bit line when the memory cell transistor is in a cut-off state. Therefore, a dynamic semiconductor memory device including a thin film SOI/MOSFET which is immune to disturbing refresh can be achieved.

Abstract: A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.multidot.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Abstract: A buried insulating layer is provided in a semiconductor substrate, in a position separated from its major surface. A LOCOS isolation film is provided in the major surface of the semiconductor substrate for isolating an active region from other active regions. A thin-film transistor is provided in the active region. The thin-film transistor comprises a gate electrode which is provided on the active region with interposition of a gate insulating layer. A pair of source/drain layers are provided in the major surface of the semiconductor substrate on both sides of the gate electrode. A high-concentration impurity layer is provided in the semiconductor substrate immediately under the buried insulating layer.

Abstract: In a semiconductor memory device, pitch of bit lines is made larger than pitch of word lines, and a storage node contact is positioned in each rectangular area surrounded by the bit lines and the word lines. The distance between centers of adjacent storage node contacts and the distance between centers of a bit line contact and an adjacent storage node contact are both made larger than the pitch of word lines. By this structure, planar area per unit memory cell can be increased, registration margin between the storage node and the storage node contact can be enlarged, short-circuit between the bit line and the storage node contact is prevented, and thus a memory cell structure of high production yield and high reliability can be realized.

Abstract: A semiconductor device having an SOI structure which involves no parasitic MOS transistor and substrate floating effect and has a planar element isolation region and, a manufacturing method therefor. In the semiconductor device, a field shield gate composed of an oxide film and a field shield gate electrode is formed to be buried under an SOI layer. As a result, it is possible to prevent generation of a parasitic transistor and substrate floating effects inherent in field shield gate while obtaining a planar element isolation structure.

Abstract: A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Abstract: An SOI-MOS transistor structure is obtained which enables prevention of a substrate floating effect, reduction of the gate capacity and the contact resistance, and connection of two or more transistors in series. A semiconductor device including this transistor includes a pair of n.sup.+ type source/drain regions and a p.sup.+ type channel potential fixing region formed by dividing an active region by a first wiring and a second wiring, and a third wiring and a fourth wiring extending from respective side portions of the wirings. Since holes stored in an effective channel region flow in the p.sup.+ type channel potential fixing region, the substrate flowing effect can be prevented. Since one region of the pair of n.sup.+ type source/drain regions is wider than the other region, the contact resistance can be decreased. Further, since the gate wirings are not connected to each other, transistors can be connected in series.

Abstract: A highly integrated semiconductor memory device having large storage capacity is obtained in which dimension loss of a storage node of a capacitive element of a memory cell from the design can be suppressed and desired capacitance value is ensured. A storage node of the capacitive element of each memory cell is formed by a third conductive layer positioned above a second conductive layer serving as the bit line, on one major surface of semiconductor substrate. Storage node is electrically connected to one of source/drain regions of the transistor element of the corresponding memory cell. The storage node is arranged between a word line to which the corresponding memory cell is connected, and another word line adjacent to said word line on the side source/drain region of the transistor element of the corresponding memory cell, and crossing a bit line which is connected to the corresponding memory cell.

Abstract: A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.multidot.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Abstract: A field shield isolating structure forms a structure for isolating elements of a semiconductor device. The field shield isolating structure includes a field shield gate insulating film and field shield electrode formed on the semiconductor substrate in separate processes to constitute a quasi-MOS transistor using impurity regions of adjacent MOS transistors. The film thickness of the field shield gate insulating film is set arbitrarily, the threshold voltage of the quasi-MOS transistor is set high, and then elements are insulated and isolated, so that the transistor is operated in the off state. The upper surface of the field shield electrode is also covered with the upper insulating film. The thicknesses of the upper insulating film and of the field shield gate insulating film is adjusted to have such values that prevent turning ON of the MOS transistor by the capacitance divided voltage. The voltage may be applied from upper conductive layers such as word lines formed above the upper insulating film.

Abstract: A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: In a semiconductor memory device, pitch of bit lines is made larger than pitch of word lines, and a storage node contact is positioned in each rectangular area surrounded by the bit lines and the word lines. The distance between centers of adjacent storage node contacts and the distance between centers of a bit line contact and an adjacent storage node contact are both made larger than the pitch of word lines. By this structure, planar area per unit memory cell can be increased, registration margin between the storage node and the storage node contact can be enlarged, short-circuit between the bit line and the storage node contact is prevented, and thus a memory cell structure of high production yield and high reliability can be realized.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: A field effect transistor comprises n type impurity regions formed spaced apart on a P type semiconductor substrate to be the source.multidot.drain regions and a T-shaped gate electrode formed on the region sandwiched by the n type impurity regions with an insulating film interposed therebetween, the gate electrode being formed of upper and lower two layers with the upper layer wider than the lower layer, wherein a n type channel region is formed between the source and the drain when the prescribed voltage is applied to the T-shaped gate electrode.

Abstract: A semiconductor device includes a first neutral impurity layer formed to a predetermined depth from a surface of a semiconductor substrate in a channel region that is interposed between source/drain regions and located below a gate electrode, and a second neutral impurity layer having a higher concentration than that of the first neutral impurity layer and formed to surround lower portions of the source/drain regions except for the channel region. Scattering of neutral impurities in the first neutral impurity layer suppresses generation of hot carriers, and the second neutral impurity layer suppresses diffusion of impurities in the source/drain regions in thermal processing. The second neutral impurity layer is formed by implanting neutral impurities obliquely after formation of the gate electrode.

Abstract: In a DRAM having stacked capacitor cells, elements are isolated by field shield isolating structure. The field shield isolating structure is formed surrounding both X and Y directions of the memory cell in the DRAM. The field shield isolating structure comprises an isolating electrode layer formed on a semiconductor substrate between adjacent memory cells with an insulating film interposed therebetween. Two impurity regions included in the adjacent memory cells and the isolating electrode layer constitute a MOS transistor. A voltage for maintaining the MOS transistor normally-off is applied to the isolating electrode layer. A portion of the stacked capacitor extends to the isolating electrode layer. One of the source/drain regions of the MOS transistor is formed in self-alignment, using a sidewall spacer formed of an insulating film on a sidewall of the field shield electrode as a mask.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor had various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.