Patents by Inventor Takahisa FURUHASHI

Takahisa FURUHASHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879293
    Abstract: There is provided a solid-state imaging device capable of reducing the number of wiring layers and achieving downsizing with flexible layout designing. The solid-state imaging device includes a first semiconductor chip including a first electrode pad, first wiring connected to a first electrode pad through a first via, and a logic circuit, which are formed therein, and a second semiconductor chip connected to the first semiconductor chip and including a second electrode pad, second wiring connected to the second electrode pad through a second via, and a pixel array, which are formed therein. The first electrode pad and the second electrode pad are bonded as being shifted from each other on a bonding surface of the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 29, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takahisa Furuhashi
  • Publication number: 20190386052
    Abstract: There is provided a solid-state imaging device capable of reducing the number of wiring layers and achieving downsizing with flexible layout designing. The solid-state imaging device includes a first semiconductor chip including a first electrode pad, first wiring connected to a first electrode pad through a first via, and a logic circuit, which are formed therein, and a second semiconductor chip connected to the first semiconductor chip and including a second electrode pad, second wiring connected to the second electrode pad through a second via, and a pixel array, which are formed therein. The first electrode pad and the second electrode pad are bonded as being shifted from each other on a bonding surface of the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: September 25, 2017
    Publication date: December 19, 2019
    Inventor: TAKAHISA FURUHASHI
  • Publication number: 20160307845
    Abstract: An object of the invention is to provide a semiconductor device with buried copper wirings having improved reliability. An interlayer insulating film including a porous Low-k film has, in a wiring trench thereof, a wiring. The wiring has a first barrier conductor film formed on the bottom surface and the side wall of the wiring trench, a second barrier conductor film formed on the first barrier conductor film, and a main conductor film formed on the second barrier conductor film and comprised mainly of copper. The first barrier conductor film and the second barrier conductor film are made of the same conductor material but the first conductor film has a density lower than that of the second barrier conductor film.
    Type: Application
    Filed: March 22, 2016
    Publication date: October 20, 2016
    Inventor: Takahisa FURUHASHI
  • Publication number: 20150357400
    Abstract: A semiconductor device having a capacitor, which provides enhanced reliability. A wiring and a capacitor are formed over an interlayer insulating film overlying a semiconductor substrate and another interlayer insulating film is formed over the interlayer insulating film so as to cover the wiring and capacitor. The capacitor includes a lower electrode overlying the interlayer insulating film, an upper electrode overlying the interlayer insulating film to cover the lower electrode at least partially, and a capacitive insulating film interposed between the lower and upper electrodes. The upper electrode and the wiring are formed from a conductive film pattern in the same layer. A plug is located under, and electrically coupled to, the lower electrode and another plug is located over the upper electrode's portion not overlapping the lower electrode in plan view and electrically coupled to the upper electrode. Another plug is located over, and electrically coupled to, the wiring.
    Type: Application
    Filed: May 13, 2015
    Publication date: December 10, 2015
    Inventors: Takahisa FURUHASHI, Masahiro MATSUMOTO
  • Patent number: 8778793
    Abstract: A barrier insulating film is constituted from a first SiCN film formed with a tetramethylsilane gas flow rate lower than usual, a second SiCN film formed over the first SiCN film and formed with a usual tetramethylsilane gas flow rate, and a SiCO film formed over the second SiCN film.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: July 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takahisa Furuhashi, Naohito Suzumura
  • Publication number: 20120228774
    Abstract: A barrier insulating film is constituted from a first SiCN film formed with a tetramethylsilane gas flow rate lower than usual, a second SiCN film formed over the first SiCN film and formed with a usual tetramethylsilane gas flow rate, and a SiCO film formed over the second SiCN film.
    Type: Application
    Filed: February 9, 2012
    Publication date: September 13, 2012
    Inventors: Takahisa FURUHASHI, Naohito Suzumura