Abstract: During adjustment of a white balance, images having different white balances are displayed respectively on a plurality of regions on the screen 201 of the display 200, based on the red video signal Rout, the green video signal Gout and the blue video signal Bout output from the gamma correction device 30. After that, an user selects any of the plurality of regions by comparing the plurality of images having the different white balances displayed on the regions A to I on the screen 201 of the display 200 and pressing a touch panel on the screen 201. The image on the selected region is displayed on the entire screen 201 of the display 200, based on the red video signal Rout, the green video signal Gout and the blue video signal Bout output from the gamma correction device 30.

Abstract: A PWM generation circuit is set so as to generate a PWM pulse signal having a frequency that is an odd number times a vertical synchronization frequency. A frequency division circuit frequency-divides the PWM pulse signal generated by the PWM generation circuit. An AND gate calculates the logical product of the PWM pulse signal generated by the PWM generation circuit and a frequency-division pulse signal outputted from the frequency division circuit. An OR gate calculates the logical sum of the PWM pulse signal generated by the PWM generation circuit and the frequency-division pulse signal outputted from the frequency division circuit. A selector outputs an output signal of the OR gate as a dimming pulse signal in a case where the set duty ratio is not less than 50%, while outputting an output signal of the AND gate as a dimming pulse signal in a case where the set duty ratio is less than 50%.

Abstract: A PWM generation circuit generates a PWM pulse signal having a variable duty ratio in order to control the luminance of a backlight. An edge detection circuit outputs a leading edge signal in response to the rise of the PWM pulse signal generated by the PWM generation circuit. A set value pulse generation circuit generates a set width pulse signal in response to the rise of the leading edge signal. The pulse width of the set width pulse signal is set so as to be larger than the minimum PWM pulse width. An OR gate calculates the logical sum of the set width pulse signal and the PWM pulse signal. An inverter circuit feeds a driving signal to a backlight on the basis of an output signal of the OR gate.

Abstract: A bit reduction apparatus prevents visual recognition of beat noise while maintaining gradation. The bit reduction apparatus changes over the bit reduction operation by executing simple discarding process and noise shaping process, on the basis of at least any one of input signal state, user's setting state, and apparatus setting state.

Abstract: A PWM generation circuit is set so as to generate a PWM pulse signal having a frequency that is an odd number times a vertical synchronization frequency. A frequency division circuit frequency-divides the PWM pulse signal generated by the PWM generation circuit. An AND gate calculates the logical product of the PWM pulse signal generated by the PWM generation circuit and a frequency-division pulse signal outputted from the frequency division circuit. An OR gate calculates the logical sum of the PWM pulse signal generated by the PWM generation circuit and the frequency-division pulse signal outputted from the frequency division circuit. A selector outputs an output signal of the OR gate as a dimming pulse signal in a case where the set duty ratio is not less than 50%, while outputting an output signal of the AND gate as a dimming pulse signal in a case where the set duty ratio is less than 50%.

Abstract: An On-Screen-Display (OSD) insert circuit includes an OSD signal generator for generating a switching signal and an analog additional image signal based on a first clock signal, an analog-to-digital converter for converting the generated additional image signal into a digital additional image signal based on a second clock signal as a sampling clock signal, a switching circuit for switching between a digital video signal and the digital additional image signal based on the switching signal, and a control-signal generator operable to generate the second clock signal. The digital video signal has a horizontal synchronizing signal. The control-signal generator is operable to reset the first clock signal with a signal having a predetermined phase difference including zero with reference to the horizontal synchronizing signal, and to generate the second clock signal so that a phase of the second clock signal is adjusted with respect to the horizontal synchronizing signal.

Abstract: A decoder includes a first bank and a second bank. The first bank is supplied with dynamic control from a microcomputer via a data bus, and the second bank is supplied with static control data from the data bus via the data bus. The dynamic control data or the static control data is read from an address in the bank designated by an address signal. The dynamic control data read from the first bank and second bank is transferred to one of a plurality of registers designated by the address signal.

Abstract: During adjustment of a white balance, images having different white balances are displayed respectively on a plurality of regions on the screen 201 of the display 200, based on the red video signal Rout, the green video signal Gout and the blue video signal Bout output from the gamma correction device 30. After that, an user selects any of the plurality of regions by comparing the plurality of images having the different white balances displayed on the regions A to I on the screen 201 of the display 200 and pressing a touch panel on the screen 201. The image on the selected region is displayed on the entire screen 201 of the display 200, based on the red video signal Rout, the green video signal Gout and the blue video signal Bout output from the gamma correction device 30.

Abstract: An On-Screen-Display (OSD) insert circuit includes an OSD signal generator for generating a switching signal and an analog additional image signal based on a first clock signal, an analog-to-digital converter for converting the generated additional image signal into a digital additional image signal based on a second clock signal as a sampling clock signal, a switching circuit for switching between a digital video signal and the digital additional image signal based on the switching signal, and a control-signal generator operable to generate the second clock signal. The digital video signal has a horizontal synchronizing signal. The control-signal generator is operable to reset the first clock signal with a signal having a predetermined phase difference including zero with reference to the horizontal synchronizing signal, and to generate the second clock signal so that a phase of the second clock signal is adjusted with respect to the horizontal synchronizing signal.

Abstract: A bit reduction apparatus prevents visual recognition of beat noise while maintaining gradation. The bit reduction apparatus changes over the bit reduction operation by executing simple discarding process and noise shaping process, on the basis of at least any one of input signal state, user's setting state, and apparatus setting state.

Abstract: A decoder includes a first bank and a second bank. The first bank is supplied with dynamic control from a microcomputer via a data bus, and the second bank is supplied with static control data from the data bus via the data bus. The dynamic control data or the static control data is read from an address in the bank designated by an address signal. The dynamic control data read from the first bank and second bank is transferred to one of a plurality of registers designated by the address signal.

Abstract: The invention presents a dot clock reproducing apparatus for automatically reproducing the dot clock easily, by setting the dot clock frequency of a video signal source, and correcting the phase difference of the dot clock occurring in the transmission route or the like, and also presents a dot clock reproducing method comprising, in dot clock reproduction, a step of sampling at a frequency different from the dot clock of video signal, a step of detecting the aliasing frequency component occurring at this time, and a step of reproducing the dot clock so as not to cause this aliasing frequency component, and as an apparatus employing such method, the invention further provides a dot clock reproducing apparatus comprising A/D converting means for receiving an adjusting signal delivered from a video signal source, and sampling this adjusting signal to convert into a digital signal, PLL means for dividing a specified synchronizing signal and generating a sampling clock for the A/D converting means, frequency anal

Abstract: A video display monitor employs interpolation which maintains sharpness in images which have large differences in signal levels of picture elements and assuring smoothness of images such as lamps which have small differences in signal levels. The difference in the signal level differences of respective adjacent picture elements is detected by delay and subtraction. A decoder produces a signal for interpolation based on the input of an interpolation coefficient and the absolute value of the interpolation coefficient which is output from an absolute value detector.

Abstract: A pixel conversion apparatus includes a sync separator for separating a sync signal from an input signal, a pixel conversion information analyzer for analyzing how to convert the number of pixels to display the input signal as an image from the input signal and a picture display area, a timing signal generator for generating a timing signal for displaying an image according to the outputs of the sync separator and the pixel conversion information analyzer, a pixel converter for processing a pixel conversion of the input signal according to the output of the timing signal generator, an interpolator for processing a pixel interpolation when the pixel to be interpolated generated by pixel conversion at the pixel converter, and a sync signal generator for generating a sync signal for displaying the input signal as an image.

Abstract: A Y/C separation apparatus separating a luminance signal and a chrominance signal from a composite color television signal includes a high band level detection circuits for detecting a high band level of each input signal and a judge circuit for controlling Y/C separation and selects one of filters to pass the input signal according to the high band levels detected by the high band level detection circuits and controls a separated chrominance signal component. As a result, when the high band level is small, a horizontal BPF is selected and even when the input signal is a black or white video signal without chrominance signal, dot interference is not conspicuous.

Abstract: A luminance and chrominance signal separating apparatus includes an A/D converter for A/D converting an input composite color television signal by a frequency of eight times of a color subcarrier frequency; a decimation filter for converting the A/D converted digital video signal into a signal with a frequency of four times of the color subcarrier frequency; a chrominance signal separating circuit for extracting a chrominance signal from the signal which was thinned-out by the frequency of four times of the color subcarrier frequency; an interpolating filter for converting the separated chrominance signal into a signal with a frequency of eight times the color subcarrier frequency and outputting a chrominance signal; a delay device for delaying the A/D converted digital video signal by a delay time which occurs when the A/D converted digital video signal passes through the decimation filter, the chrominance signal separator and the interpolating filter; and a subtracting circuit for subtracting the chrominanc

Abstract: A PAL system demodulator capable of delivering high quality color signals even in the cases of poor vertical correlation comprising 1H delay line 1 delaying the chroma signal by one horizontal period, 1H delay-line 2 delaying a reference signal by one horizontal period wherein the output of the 1H delay line 1 is defined by reference signal, color demodulating circuit 3 canceling hue error by conducting an operation between the scanning lines covering from the input and the output of the 1H delay line 1, color-demodulating circuit 4 canceling the hue error by conducting an operation between the scanning lines covering from the input and the output of the 1H delay line 2, vertical correlation detecting circuit 5 detecting the vertical correlation between the chroma signal of the reference signal and the chroma signal of the adjoining line or the chroma signal of the adjoining line separated by one-line, and selector 6 selecting the output of the color demodulating circuit 3 or the output of color demodulating

Abstract: A device that separates a luminance signal and a chrominance signal from an input composite color television signal, suppressing cross color interference and keeping a good color transient characteristic, by selecting characteristics of the color bandpass filters according to a vertical correlation value after obtaining a chrominance signal at an adaptive type comb filters.

Abstract: A device that separates a luminance signal and a chrominance signal from an input composite color television signal, suppressing cross color interference and keeping a good color transient characteristic, by selecting characteristics of the color bandpass filters according to a vertical correlation value after obtaining a chrominance signal at an adaptive type comb filters.

Abstract: An adaptive type color demodulation apparatus for the PAL system includes a first color demodulating circuit (PAL-D) for demodulating a PAL system chrominance signal between scanning lines and a second color demodulating circuit (PAL-S) for demodulating the PAL system chrominance signal on a scanning line. Also included is a vertical correlation detecting circuit for detecting a vertical correlation between chrominance signals which are separated by two horizontal periods and a selector for selecting either an output of the first color demodulating circuit or an output of the second color demodulating circuit in response to the detected result of the correlation detecting circuit. Accordingly, hue distortion of the chrominance signal which occurs during signal transmission is cancelled even if the phase distortion is large and a precise color signal is demodulated even if there is no correlation between adjacent scanning lines.