Abstract: A semiconductor device includes a SAW device chip. The SAW device chip is provided on a passive element chip in which a passive element circuit including a transmission line is formed on a semi-insulating compound substrate having one surface set to have a ground potential electrode. In the semiconductor device, even when the width of the transmission line is increased, a high characteristic impedance can be maintained by increasing the thickness of the substrate. This can reduce the resistance of the transmission line and can facilitate matching with the SAW device.

Abstract: A semiconductor device includes a SAW device chip. The SAW device chip is provided on a passive element chip in which a passive element circuit including a transmission line is formed on a semi-insulating compound substrate having one surface set to have a ground potential electrode. In the semiconductor device, even when the width of the transmission line is increased, a high characteristic impedance can be maintained by increasing the thickness of the substrate. This can reduce the resistance of the transmission line and can facilitate matching with the SAW device.

Abstract: An amplifier circuit includes a first FET of an enhancement type having a gate supplied with an input signal and a gate bias voltage and a drain via which an amplified output signal is output, and a second FET of the enhancement type having a drain connected to a drain voltage source, a source connected to the drain of the first FET, and a gate supplied with a control signal for controlling the drain voltage supplied to the first FET.

Abstract: A semiconductor amplifying circuit of the present invention comprises: an amplifying field effect transistor device having a gate supplied with an input signal and a drain for outputting an amplified output signal; and a bias circuit for supplying a bias voltage to said gate of said amplifying transistor device. The bias circuit includes: a first bias voltage generator having a first dummy field effect transistor device formed on a same substrate as said amplifying transistor device is formed, and a voltage feedback bias circuit for supplying a bias voltage to a gate of said first dummy transistor device; and a second bias voltage generator for supplying a lower potential to said voltage feedback bias circuit when a drain current of said field effect transistor device increases, and supplying a higher potential to said voltage feedback bias circuit when said drain current decreases.

Abstract: A chip carrier for a semiconductor chip, the chip having a specified thickness and lateral configuration and size. A conductive holder of the carrier has a main surface including a chip mounting surface portion for mounting the semiconductor chip thereon and a peripheral surface portion surrounding the mounting surface portion. An insulative collar member is affixed to the peripheral surface portion and has inner wall surfaces surrounding the mounting surface portion and defining a recess, of depth and lateral configuration and size dimensions respectively corresponding to those of the chip, for receiving therein and thereby positioning the chip on the conductive holder.

Abstract: A semiconductor device having a built-in capacitor comprises a substrate, an internal electrode provided on a top side of the substrate, a dielectric film provided so as to cover the internal electrode for establishing a predetermined capacitance, a surface electrode provided on the dielectric film so as to make a contact therewith, a plurality of through holes formed in the substrate in correspondence to the internal electrode so as to extend from a bottom side to the top side, and a back-side electrode provided on the bottom side of the substrate including the through holes so as to make a contact with the internal electrode through the through holes.

Abstract: A metal-semiconductor field effect transistor device has an active layer formed on a first main surface of a semiconductor substrate with a first gate electrode provided on the active layer in Schottky contact therewith and source and drain electrodes provided on opposite sides of the first gate electrode and in ohmic contact with the active layer so as to define corresponding source and drain regions in the active layer with an active region of the active layer extending therebetween. A second gate electrode including first and second portions is provided in Schottky contact on the active layer, respectively on the exposed surface portion segments thereof intermediate the opposite sides of the first gate electrode and the respective drain and source electrodes associated with the first gate electrode.