Abstract: A compiling apparatus includes an instruction-sequence-hierarchy-graph generating unit that generates an instruction sequence hierarchy graph by arraying unit graphs, to each of which a data path realized by a plurality of microinstructions included in one instruction sequence is to be allocated and in each of which function units included in a target processor are a node and a data line between the function units is an edge, to correspond to an execution order of a plurality of instruction sequences and by connecting arrayed unit graphs with an edge corresponding to a hardware path capable of establishing a data path across the instruction sequences; a data path allocating unit that allocates a data path to each of the unit graphs constituting the instruction sequence hierarchy graph; and an object program output unit that generates an instruction sequence group based on the data path allocated to the instruction sequence hierarchy graph.

Abstract: A microprocessor that can perform sequential processing in data array unit includes: a load store unit that loads, when a fetched instruction is a load instruction for data, a data sequence including designated data from a data memory in memory width unit and specifies, based on an analysis result of the instruction, data scheduled to be designated in a load instruction in future; and a data temporary storage unit that stores use-scheduled data as the data specified by the load store unit.

Abstract: An input unit that sequentially writes a digital image signal to be input in a first buffer while counting number of pixels of the digital image signal, and that writes the written digital image signal in a second buffer; and a command fetching/issuing unit that calculates a position of a pixel based on process delay information that is added to an image processing command and that indicates a delay amount required until image processing by the command is started since the input of the digital image signal, and a counter value indicating the number of pixels, and that issues the image processing command when the position of the pixel is in a valid area are included. Image processing is performed on pixels written in the second buffer based on the issued image processing command.

Abstract: An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

Abstract: An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

Abstract: There is provided with an image coding method including: splitting an image into a plurality of block images each having plural pixels; performing a Discrete Cosine Transform (DCT) processing on the block image to calculate DCT coefficients from the block image; determining whether the block image is in a flat state or non-flat state depending on the DCT coefficients calculated from the block image; specifying as quantization step sizes for first DCT coefficients which are DCT coefficients equivalent to one-dimensional DCT coefficient out of the calculated DCT coefficients, adjusting step sizes equal to or smaller than values of the first DCT coefficients and as quantization step sizes for second DCT coefficients other than the first DCT coefficients out of the calculated DCT coefficients, standard step sizes given beforehand, when the block image is in the flat state; and quantizing the calculated DCT coefficients with respective quantization step sizes specified.

Abstract: A memory controller controls a memory access to each memory region out of one or more memory regions in SIMD unit. The memory controller includes: a pointer-calculation hardware unit that increments by unit SIMD a value of an access control pointer corresponding to each of the memory regions at different timings corresponding to an access mode set beforehand in each memory region; and a memory-access-control hardware unit that calculates an access destination address in each of the memory regions based on a value of an access control pointer in the memory region, and causes a memory access in SIMD unit to be performed to the calculated access destination address.

Abstract: A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

Abstract: An image coding device includes a block dividing unit that divides image data into blocks, so as to generate block data, each of the blocks being formed with a plurality of pixels, a DCT unit that carries out a discrete cosine transform on the block data, so as to generate DCT coefficients, a feature analyzing unit that analyzes the block data, so as to generate feature data, a quantization parameter generating unit that refers to the block data and the feature data, and generates a quantization matrix, a quantizing unit that quantizes the DCT coefficients with the use of the quantization matrix, so as to generate quantized data, and a variable-length coding unit that performs variable-length coding on the quantized data, so as to generate variable-length coded data.

Abstract: An edge information detection section detects edge information corresponding to a spatial change in a pixel value in a predetermined region by using a two-dimensional first differential filter with respect to an input image signal. An edge intensity detection section detects an edge intensity by using a first threshold value with respect to the edge information detected in the predetermined region. A flatness detection section detects a degree of flatness by using a second threshold value smaller than the first threshold value with respect to the edge information detected in the predetermined region. A determination section generates a two or more valued determination signal by determining the edge information in the predetermined region from the edge intensity and the degree of flatness.

Abstract: An embodiment of the present invention is an image processing device which determines a reference frame for moving image compressing by inter-frame prediction, for each frame of a moving image, includes: a comparing section configured to compare, between frames of the moving image, sums of brightnesses of pixels in the respective frames, sums of brightnesses of pixels on a line or lines in a first direction of the respective frames, and sums of brightnesses of pixels on a line or lines in a second direction of the respective frames respectively, the second direction being nonparallel to the first direction; a judging section configured to judge whether or not there is a flash in each frame, based on a comparison result by the comparing section; and a determining section configured to determine a frame before the start of the flash to be a reference frame of a frame after the end of the flash, based on a judgement result by the judging section.

Abstract: There is provided with an image coding method including: splitting an image into a plurality of block images each having plural pixels; performing a Discrete Cosine Transform (DCT) processing on the block image to calculate DCT coefficients from the block image; determining whether the block image is in a flat state or non-flat state depending on the DCT coefficients calculated from the block image; specifying as quantization step sizes for first DCT coefficients which are DCT coefficients equivalent to one-dimensional DCT coefficient out of the calculated DCT coefficients, adjusting step sizes equal to or smaller than values of the first DCT coefficients and as quantization step sizes for second DCT coefficients other than the first DCT coefficients out of the calculated DCT coefficients, standard step sizes given beforehand, when the block image is in the flat state; and quantizing the calculated DCT coefficients with respective quantization step sizes specified.

Abstract: A moving picture processor including an evaluator configured to evaluate whether terminal points of motion vectors consecutively detected in a current picture and a reference picture different from the current picture in terms of time are in a determination area having a center at a terminal point of a reference vector. A unifier is configured to unify a group of motion vectors consecutively evaluated to be in the determination area, and to reset the motion vector evaluated to be outside the determination area as the reference vector.

Abstract: A moving picture processor includes a first detector configured to detect a reference block most similar to a target block for which motion is to be detected and which is set in a current picture, and to generate a first motion vector candidate indicating a relative position between the target block and the reference block. A second detector is configured to detect a first reference area most similar to a first target area obtained by combining the target block and a first adjacent block adjacent to the target block, and to generate a second motion vector candidate indicating a relative position between the first target area and the first reference area. A determination circuit is configured to determine a motion vector for the target block, based on the first and second motion vector candidates.