Patents by Inventor Takahisa Yoshida

Takahisa Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220153609
    Abstract: A method for decomposing and removing a pollutant includes: confining, in a small sealable container, a waste containing the pollutant to be processed and liquid for dilution together with gas containing oxygen or air; disposing the small sealable container in a processing chamber of a high-temperature and high-pressure processing device and keeping the small sealable container at an elevated temperature after the confining; and lowering a temperature in the processing chamber after the disposing. The disposing and the lowering are performed under a state where the small sealable container is pressurized from outside by increasing a pressure in the processing chamber.
    Type: Application
    Filed: November 5, 2021
    Publication date: May 19, 2022
    Applicants: National Institute of Advanced Industrial Science and Technology, HIRAYAMA MANUFACTURING CORPORATION
    Inventors: Tetsushi SUYAMA, Mamoru KAWAHARASAKI, Takahisa YOSHIDA, Chikashi YOSHINAGA
  • Patent number: 8884306
    Abstract: A semiconductor device includes a supporting substrate, a conductive layer placed on the supporting substrate, and at least one group III nitride semiconductor layer placed on the conductive layer. Of the group III nitride semiconductor layers, a conductive-layer-neighboring group III nitride semiconductor layer has n type conductivity, dislocation density of at most 1×107 cm?2, and oxygen concentration of at most 5×1018 cm?3. Thus, an n-down type device having a semiconductor layer of high crystallinity can be provided.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: November 11, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Kuniaki Ishihara, Akihiro Hachigo, Takahisa Yoshida, Masaki Ueno, Makoto Kiyama
  • Patent number: 8445925
    Abstract: A semiconductor optical device includes: a group III nitride semiconductor substrate having a primary surface of a first orientation; a first group III nitride semiconductor laminate including a first active layer disposed on a first region of the primary surface; a group III nitride semiconductor thin film having a surface, which has a second orientation different from the first orientation, disposed on a second region, the second region being different from the first region; a junction layer provided between the second region and the group III nitride semiconductor thin film; and a second group III nitride semiconductor laminate including a second active layer and disposed on the surface of the group III nitride semiconductor thin film. The first and second active layers include first and second well layers containing In, respectively, and the emission wavelengths of the first and second well layers are different from each other.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: May 21, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takahisa Yoshida, Yohei Enya, Takashi Kyono, Masaki Ueno
  • Publication number: 20130051418
    Abstract: A group-III nitride semiconductor laser device includes an n-type nitride semiconductor region, an active layer provided over the n-type nitride semiconductor region, a first p-type nitride semiconductor region provided over the active layer, a current confinement layer which is provided over the first p-type nitride semiconductor region and has an opening extending in a optical cavity direction, and a second p-type nitride semiconductor region re-grown on the first nitride semiconductor region and the current confinement layer after the formation of the opening of the current confinement layer. The interface between the first p-type nitride semiconductor region and the second p-type nitride semiconductor region includes a semi-polar plane. At least one of the first or second p-type semiconductor regions includes a highly doped p-type semiconductor layer forming an interface with the first and second p-type semiconductor regions and have a p-type impurity level of 1×1020 cm?3 or greater.
    Type: Application
    Filed: July 24, 2012
    Publication date: February 28, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takamichi SUMITOMO, Masaki UENO, Yusuke YOSHIZUMI, Takahisa YOSHIDA, Masahiro ADACHI
  • Publication number: 20120273816
    Abstract: A semiconductor optical device includes: a group III nitride semiconductor substrate having a primary surface of a first orientation; a first group III nitride semiconductor laminate including a first active layer disposed on a first region of the primary surface; a group III nitride semiconductor thin film having a surface, which has a second orientation different from the first orientation, disposed on a second region, the second region being different from the first region; a junction layer provided between the second region and the group III nitride semiconductor thin film; and a second group III nitride semiconductor laminate including a second active layer and disposed on the surface of the group III nitride semiconductor thin film. The first and second active layers include first and second well layers containing In, respectively, and the emission wavelengths of the first and second well layers are different from each other.
    Type: Application
    Filed: March 29, 2012
    Publication date: November 1, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takahisa YOSHIDA, Yohei ENYA, Takashi KYONO, Masaki UENO
  • Publication number: 20120205661
    Abstract: A semiconductor device includes a supporting substrate, a conductive layer placed on the supporting substrate, and at least one group III nitride semiconductor layer placed on the conductive layer. Of the group III nitride semiconductor layers, a conductive-layer-neighboring group III nitride semiconductor layer has n type conductivity, dislocation density of at most 1×107 cm?2, and oxygen concentration of at most 5×1018 cm?3. Thus, an n-down type device having a semiconductor layer of high crystallinity can be provided.
    Type: Application
    Filed: January 19, 2012
    Publication date: August 16, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takashi KYONO, Kuniaki Ishihara, Akihiro Hachigo, Takahisa Yoshida, Masaki Ueno, Makoto Kiyama