Patents by Inventor Takahito Harada

Takahito Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230343682
    Abstract: A wire protecting part partially encloses a first lead frame and a second lead frame and has an enclosing surface from which the first and second lead frames protrude. The enclosing surface is parallel to semiconductor chips, and includes a water stop part protruding, from the enclosing surface, between the first and second lead frames.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 26, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro MARUYAMA, Yoshinori ODA, Takahito HARADA
  • Publication number: 20230282632
    Abstract: A semiconductor module, including a first main wiring line connecting portion and a second main wiring line connecting portion, and a main output wiring line connecting portion is provided. The circuit board includes a circuit region in which the first circuit and the second circuit are arranged alongside each other in the first direction, and a first connecting region and a second connecting region arranged sandwiching the circuit region in a second direction orthogonal to the first direction. The first main wiring line connecting portion and the second main wiring line connecting portion are provided in the first connecting region, and the main output wiring line connecting portion is provided in the second connecting region.
    Type: Application
    Filed: January 23, 2023
    Publication date: September 7, 2023
    Inventors: Ryo NOMAGUCHI, Takahito HARADA
  • Publication number: 20230014848
    Abstract: A semiconductor device includes first semiconductor chips that each include a first control electrode and a first output electrode, second semiconductor chips each include a second control electrode and a second output electrode, first and second input circuit patterns on which the first and second input electrodes are disposed, respectively, first and second control circuit patterns electrically connected to the first and second control electrodes, respectively, first and second resistive elements, and a first inter-board wiring member. The first control electrodes and first resistive element are electrically connected via the first control circuit pattern, the second control electrodes and second resistive element are electrically connected via the second control circuit pattern, and at least one of the first output electrodes and at least one of the second output electrodes are electrically connected to each other via the first inter-board wiring member.
    Type: Application
    Filed: May 31, 2022
    Publication date: January 19, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro MARUYAMA, Norihiro KOMIYAMA, Kunio KOBAYASHI, Yuto KOBAYASHI, Takahito HARADA, Hirohisa OYAMA, Masahiro SASAKI, Ryousuke USUI
  • Patent number: 9673117
    Abstract: A semiconductor module includes a plurality of insulating circuit boards including semiconductor chips, each of the plurality of insulating circuit boards including a first outer edge among outer edges of the insulating circuit board facing an adjacent insulating circuit board of the plurality of insulating circuit boards, and a second outer edge among the outer edges excluding the first outer edge; a resin frame body having a crosspiece abutting against the first outer edges, and a frame element abutting against the second outer edges; a conductive component striding over the crosspiece to electrically connect the insulating circuit boards to each other; and an upper lid having a lid element covering an opening disposed at an upper part of the resin frame body and a partition protruding from a face of the lid element facing the insulating circuit boards to abut against a part of the crosspiece.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: June 6, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro Maruyama, Takahito Harada
  • Patent number: 9530707
    Abstract: A semiconductor module includes a printed circuit board having an insulating plate, first and fourth wiring layers disposed on a principal surface of the insulating plate, second and third wiring layers disposed on another surface opposite to the principal surface, a first via disposed in the insulating plate and electrically and mechanically connected to the first and third wiring layers, and a second via disposed in the insulating plate and electrically and mechanically connected to the second and fourth wiring layers; a first insulating substrate disposed with a first circuit plate; a second insulating substrate disposed with a second circuit plate; a first semiconductor chip; a second semiconductor chip; a first heat release member fixed between the third wiring layer and the third circuit plate; and a second heat release member fixed between the fourth wiring layer and the first circuit plate.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: December 27, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takahito Harada
  • Publication number: 20160118310
    Abstract: A semiconductor module includes a plurality of insulating circuit boards including semiconductor chips, each of the plurality of insulating circuit boards including a first outer edge among outer edges of the insulating circuit board facing an adjacent insulating circuit board of the plurality of insulating circuit boards, and a second outer edge among the outer edges excluding the first outer edge; a resin frame body having a crosspiece abutting against the first outer edges, and a frame element abutting against the second outer edges; a conductive component striding over the crosspiece to electrically connect the insulating circuit boards to each other; and an upper lid having a lid element covering an opening disposed at an upper part of the resin frame body and a partition protruding from a face of the lid element facing the insulating circuit boards to abut against a part of the crosspiece.
    Type: Application
    Filed: January 7, 2016
    Publication date: April 28, 2016
    Inventors: Rikihiro MARUYAMA, Takahito HARADA
  • Publication number: 20160027711
    Abstract: A semiconductor module includes a printed circuit board having an insulating plate, first and fourth wiring layers disposed on a principal surface of the insulating plate, second and third wiring layers disposed on another surface opposite to the principal surface, a first via disposed in the insulating plate and electrically and mechanically connected to the first and third wiring layers, and a second via disposed in the insulating plate and electrically and mechanically connected to the second and fourth wiring layers; a first insulating substrate disposed with a first circuit plate; a second insulating substrate disposed with a second circuit plate; a first semiconductor chip; a second semiconductor chip; a first heat release member fixed between the third wiring layer and the third circuit plate; and a second heat release member fixed between the fourth wiring layer and the first circuit plate.
    Type: Application
    Filed: October 7, 2015
    Publication date: January 28, 2016
    Inventor: Takahito HARADA
  • Patent number: 8692350
    Abstract: A semiconductor device, and method of manufacturing the device, having a p type diffusion layer; a V-groove including a bottom surface parallel to the rear surface and exposing the p type diffusion layer and a tapered side surface rising from the bottom surface; a p type semiconductor layer on the rear surface surrounded by the tapered side surface of the V-groove; and a p type isolation layer formed on the side surface and electrically connecting the p type diffusion layer on the front surface and the p type semiconductor layer on the rear surface. The V-groove has a chamfered configuration around the intersection between a corner part of the side surface and the bottom surface of the V-groove. An object is to prevent performance degradation due to stress concentration at the corner part of a recessed part caused by thermal history in soldering.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: April 8, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Haruo Nakazawa, Takahito Harada, Fumio Shigeta, Kyohei Fukuda
  • Publication number: 20120098085
    Abstract: A semiconductor device, and method of manufacturing the device, having a p type diffusion layer; a V-groove including a bottom surface parallel to the rear surface and exposing the p type diffusion layer and a tapered side surface rising from the bottom surface; a p type semiconductor layer on the rear surface surrounded by the tapered side surface of the V-groove; and a p type isolation layer formed on the side surface and electrically connecting the p type diffusion layer on the front surface and the p type semiconductor layer on the rear surface. The V-groove has a chamfered configuration around the intersection between a corner part of the side surface and the bottom surface of the V-groove. An object is to prevent performance degradation due to stress concentration at the corner part of a recessed part caused by thermal history in soldering.
    Type: Application
    Filed: October 19, 2011
    Publication date: April 26, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo NAKAZAWA, Takahito Harada, Fumio Shigeta, Kyohei Fukuda