Abstract: A path switching FET and a shunt FET are separated from each other by a capacitor. The gates of the path switching FET and the shunt FET are controlled using an inverter circuit having a first internal power supply voltage (e.g., 2.5 V) as a power supply. The sources and drains of the path switching FET and the shunt FET are controlled using an inverter circuit having a second internal power supply voltage (e.g., 1.25 V) which is smaller than the first internal power supply voltage, as a power supply.

Abstract: A path switching FET and a shunt FET are separated from each other by a capacitor. The gates of the path switching FET and the shunt FET are controlled using an inverter circuit having a first internal power supply voltage (e.g., 2.5 V) as a power supply. The sources and drains of the path switching FET and the shunt FET are controlled using an inverter circuit having a second internal power supply voltage (e.g., 1.25 V) which is smaller than the first internal power supply voltage, as a power supply.

Abstract: A diode-switch logic circuit of the present invention is configured such that: at least one of paths between a common input-output terminal and respective individual input-output terminals is caused to become a conducting state; control voltages of control terminals are respectively applied to gates of path switching FET stages; logic synthesis voltages of the control voltages of the control terminals are respectively applied to gates of shunt FET stages; and each of the logic synthesis voltages is generated by a logical product of a logical negation of the control voltage applied to one shunt FET stage and a logical sum of the control voltages respectively applied to the remaining shunt FET stages.

Abstract: Provided is a transmission circuit which allows smooth switching of the operation mode when switching the operation mode of the transmission circuit. A power amplifier 14 includes: a first input terminal to which a direct-current voltage or a voltage in accordance with an amplitude signal M is supplied; a second input terminal to which an output signal from a first variable gain amplifier 171 or an output signal from a second variable gain amplifier 172 is inputted; and a third input terminal to which an output signal from a first bias circuit 15 or an output signal from a second bias circuit 16 is inputted. A control section 11 switches the operation mode of the transmission circuit so that at least one of the first input terminal, the second input terminal, and the third input terminal of the power amplifier is prevented from being in a no input state.

Abstract: A high frequency switch circuit including: a first rectifier circuit including at least one rectifier element having one end connected between the gate terminal of a first MOSFET circuit and a first control terminal and the other end connected to ground, and a second rectifier circuit including at least one rectifier element having one end connected between the gate terminal of a second MOSFET circuit and a second control terminal and the other end connected to ground. The circuit further includes a connecting section connecting the forward-current input terminal side of at least one of the rectifier elements of the first rectifier circuit and one of the main terminal sides of the first MOSFET circuit, and connecting the forward-current input terminal side of at least one of the rectifier elements of the second rectifier circuit and one of the main terminal sides of the second MOSFET circuit.

Abstract: Provided is a transmission circuit which allows smooth switching of the operation mode when switching the operation mode of the transmission circuit. A power amplifier 14 includes: a first input terminal to which a direct-current voltage or a voltage in accordance with an amplitude signal M is supplied; a second input terminal to which an output signal from a first variable gain amplifier 171 or an output signal from a second variable gain amplifier 172 is inputted; and a third input terminal to which an output signal from a first bias circuit 15 or an output signal from a second bias circuit 16 is inputted. A control section 11 switches the operation mode of the transmission circuit so that at least one of the first input terminal, the second input terminal, and the third input terminal of the power amplifier is prevented from being in a no input state.

Abstract: A semiconductor device includes a layered region (104) formed in a semiconductor substrate (101) of a first conductivity type, and an electrode pad (106) formed on the semiconductor substrate with an interlayer insulating film (105) interposed therebetween and placed above the layered region. The layered region includes a first impurity diffusion region (102), a second impurity diffusion region (103) formed on the first impurity diffusion region, and a third impurity diffusion region (102x) formed on the first impurity diffusion region and surrounding a periphery of the second impurity diffusion region. a conductivity type of the first impurity diffusion region and a conductivity type of the third impurity diffusion region are a second conductivity type, and a conductivity type of the second impurity diffusion region is the first conductivity type.

Abstract: The transmission apparatus according to the present invention can reduce transmission output noise leaking into the receiving apparatus even when the transmission apparatus is applied to wireless equipment using the W-CDMA scheme. Transmission apparatus (100) has bypass circuit (101) and bypass control circuit (103) that inputs an RF phase signal to power amplifier (14) via amplitude adjustment circuit (16) when bypass circuit (101) and power amplifier (14) are operated in non-saturation mode, and that inputs the RF phase signal to power amplifier (14) via bypass circuit (101) when power amplifier (14) is operated in saturation mode.

Abstract: A semiconductor device includes a layered region (104) formed in a semiconductor substrate (101) of a first conductivity type, and an electrode pad (106) formed on the semiconductor substrate with an interlayer insulating film (105) interposed therebetween and placed above the layered region. The layered region includes a first impurity diffusion region (102), a second impurity diffusion region (103) formed on the first impurity diffusion region, and a third impurity diffusion region (102x) formed on the first impurity diffusion region and surrounding a periphery of the second impurity diffusion region. a conductivity type of the first impurity diffusion region and a conductivity type of the third impurity diffusion region are a second conductivity type, and a conductivity type of the second impurity diffusion region is the first conductivity type.

Abstract: A variable attenuator, used with high frequency, provides large variable attenuation per stage. The variable attenuator includes: a MOSFET having a gate, a drain, a source, and a body; an attenuation control circuit; and a temperature characteristics compensation circuit. The attenuation control circuit supplies a control voltage to the gate, the drain, and the source. The temperature characteristics compensation circuit supplies a temperature compensation voltage to the body. An input terminal and an output terminal are connected to the drain and the source of the MOSFET. The temperature characteristics compensation circuit, in accordance with an operating temperature of the MOSFET, controls a voltage to be supplied to the body and adjusts, based on a relation between a body voltage and a gate voltage, a resistance value of a current flowing between the input terminal and the output terminal.

Abstract: A variable attenuator, used with high frequency, in which variable attenuation per stage is large, is provided. The variable attenuator includes: a MOSFET 12 having a gate, a drain, a source, and a body; an attenuation control circuit 14; and a temperature characteristics compensation circuit 21. The attenuation control circuit 14 supplies a control voltage to the gate, the drain, and the source. The temperature characteristics compensation circuit 21 supplies a temperature compensation voltage to the body. An input terminal and an output terminal are connected to the drain and the source of the MOSFET 12. The temperature characteristics compensation circuit 21, in accordance with an operating temperature of the MOSFET 12, controls a voltage to be supplied to the body and adjusts, based on a relation between a body voltage and a gate voltage, a resistance value of a current flowing between the input terminal and the output terminal.

Abstract: The transmission apparatus according to the present invention can reduce transmission output noise leaking into the receiving apparatus even when the transmission apparatus is applied to wireless equipment using the W-CDMA scheme. Transmission apparatus (100) has bypass circuit (101) and bypass control circuit (103) that inputs an RF phase signal to power amplifier (14) via amplitude adjustment circuit (16) when bypass circuit (101) and power amplifier (14) are operated in non-saturation mode, and that inputs the RF phase signal to power amplifier (14) via bypass circuit (101) when power amplifier (14) is operated in saturation mode.

Abstract: A variable gain amplifier is provided that scarcely suffers disturbance or interference such as carrier leak from other circuit blocks even when a plurality of circuits are constructed on the same semiconductor substrate, and that has low output impedance fluctuation. For the purpose of this, in a variable gain amplifier, the ground terminal of a signal amplifying transistor is connected to a dedicated grounding pad to which the other circuit blocks are not connected, so that disturbance or interference such as carrier leak from other circuit blocks is reduced. Further, the ground terminal of an output impedance compensation circuit is also connected to the same grounding pad described above, so that further disturbance or interference is avoided. As a result, the circuit scarcely suffers disturbance or interference such as carrier leak from other circuit blocks, so that output impedance fluctuation is reduced.