Patents by Inventor Takahito Nakazawa
Takahito Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240077712Abstract: Provided is an efficient method for attaching a tissue section. In the invention, one of problems is solved by changing attachment conditions of the tissue section depending on an organ from which the tissue section is derived. A technique of achieving good adhesiveness between a microscope slide and a section by introducing unevenness on a front surface of the microscope slide using reactive ion etching as one of the attachment conditions is provided. Further, a technique of optimizing the attachment of the section using a machine learning technique or the like is provided.Type: ApplicationFiled: October 16, 2019Publication date: March 7, 2024Inventors: Toru FUJIMURA, Takahito HASHIMOTO, Shigehiko KATO, Eiko NAKAZAWA, Masahiko AJIMA, Akira SAWAGUCHI
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Patent number: 8241999Abstract: A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region.Type: GrantFiled: February 16, 2010Date of Patent: August 14, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takafumi Ikeda, Takahito Nakazawa, Hideaki Maekawa, Yuuichi Tatsumi, Toshifumi Minami
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Publication number: 20100237438Abstract: A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region.Type: ApplicationFiled: February 16, 2010Publication date: September 23, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Takafumi IKEDA, Takahito Nakazawa, Hideaki Maekawa, Yuuichi Tatsumi, Toshifumi Minami
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Patent number: 6774011Abstract: A pickup device comprises a thrusting mechanism, a carrying mechanism and a controller. The thrusting mechanism is configured to thrust the chips sequentially by using pins from a back side of the adhesive tape with the adhesive tape between the chips and the pins so as to peel the chips off the adhesive tape. The carrying mechanism is configured to sequentially absorb the chips with use of a collet, hold the chips to be absorbed until the chips are peeled off the adhesive tape, thereafter pick the chips up by ascending the collet in order to be carried the chips to a subsequent process stage. The controller is configured to controlling the thrust of the chip by thrusting mechanism, the controller control an ascend time and a descend time of the pins, and keeping a predetermined period of a time when the pins arrive at their peak.Type: GrantFiled: August 3, 2001Date of Patent: August 10, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Takahito Nakazawa, Tetsuya Kurosawa, Hideo Numata, Shinya Takyu
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Patent number: 6448665Abstract: In order to suppress the warp of a semiconductor package of an over-coat structure, when thermal expansion coefficient, Young's modulus and thickness of the wiring substrate are &agr;s, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of the resin layer are &agr;r, Er and Hr, respectively, the value R of (&agr;r·Er·Hr)/(&agr;s·Es·Hs) is set to be approximately 0.6 or more. With adoption of such a configuration, stress exerting on a semiconductor package can be effectively alleviated, and coplanarity of the semiconductor package can be improved.Type: GrantFiled: October 14, 1998Date of Patent: September 10, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Takahito Nakazawa, Yoshiaki Sugizaki
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Patent number: 6379484Abstract: An apparatus is provided for manufacturing a semiconductor package of the type in which a gap between a semiconductor chip and a mount board is filled with a resin. The apparatus includes resin supply means for supplying the resin along one side of the semiconductor chip, and resin supply control means for controlling the amount of resin supplied by the resin supply means such that more resin is supplied near the central portion of the semiconductor chip than near the end portions of the semiconductor chip. Also provided is a method that includes the steps of connecting the semiconductor chip and the mount board, and supplying the resin along one side of the semiconductor chip in such a manner that more resin is supplied near a central portion of the semiconductor chip than near the end portions of the semiconductor chip.Type: GrantFiled: December 5, 2000Date of Patent: April 30, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Takahito Nakazawa, Hiroshi Nomura, Yumiko Ohshima
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Publication number: 20020019074Abstract: A pickup device comprises a thrusting mechanism, a carrying mechanism and a controller. The thrusting mechanism is configured to thrust the chips sequentially by using pins from a back side of the adhesive tape with the adhesive tape between the chips and the pins so as to peel the chips off the adhesive tape. The carrying mechanism is configured to sequentially absorb the chips with use of a collet, hold the chips to be absorbed until the chips are peeled off the adhesive tape, thereafter pick the chips up by ascending the collet in order to be carried the chips to a subsequent process stage. The controller is configured to controlling the thrust of the chip by thrusting mechanism, the controller control an ascend time and a descend time of the pins, and keeping a predetermined period of a time when the pins arrive at their peak.Type: ApplicationFiled: August 3, 2001Publication date: February 14, 2002Applicant: Kabushiki Kaisha Toshiba.Inventors: Takahito Nakazawa, Tetsuya Kurosawa, Hideo Numata, Shinya Takyu
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Publication number: 20010020736Abstract: In order to suppress the warp of a semiconductor package of an over-coat structure, when thermal expansion coefficient, Young's modulus and thickness of the wiring substrate are &agr;s, Es and Hs, respectively, and thermal expansion coefficient, Young's modulus and thickness of the resin layer are &agr;r, Er and Hr, respectively, the value R of (&agr;r·Er·Hr)/(&agr;s·Es·Hs) is set to be approximately 0.6 or more. With adoption of such a configuration, stress exerting on a semiconductor package can be effectively alleviated, and coplanarity of the semiconductor package can be improved.Type: ApplicationFiled: May 8, 2001Publication date: September 13, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takahito Nakazawa, Yoshiaki Sugizaki
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Publication number: 20010000754Abstract: An apparatus is provided for manufacturing a semiconductor package of the type in which a gap between a semiconductor chip and a mount board is filled with a resin. The apparatus includes resin supply means for supplying the resin along one side of the semiconductor chip, and resin supply control means for controlling the amount of resin supplied by the resin supply means such that more resin is supplied near the central portion of the semiconductor chip than near the end portions of the semiconductor chip. Also provided is a method that includes the steps of connecting the semiconductor chip and the mount board, and supplying the resin along one side of the semiconductor chip in such a manner that more resin is supplied near a central portion of the semiconductor chip than near the end portions of the semiconductor chip.Type: ApplicationFiled: December 5, 2000Publication date: May 3, 2001Applicant: Kabushiki Kaisha ToshibaInventors: Takahito Nakazawa, Hiroshi Nomura, Yumiko Ohshima
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Patent number: 6191024Abstract: An apparatus is provided for manufacturing a semiconductor package of the type in which a gap between a semiconductor chip and a mount board is filled with a resin. The apparatus includes resin supply means for supplying the resin along one side of the semiconductor chip, and resin supply control means for controlling the amount of resin supplied by the resin supply means such that more resin is supplied near the central portion of the semiconductor chip than near the end portions of the semiconductor chip. Also provided is a method that includes the steps of connecting the semiconductor chip and the mount board, and supplying the resin along one side of the semiconductor chip in such a manner that more resin is supplied near a central portion of the semiconductor chip than near the end portions of the semiconductor chip.Type: GrantFiled: April 20, 1999Date of Patent: February 20, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Takahito Nakazawa, Hiroshi Nomura, Yumiko Ohshima
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Patent number: 6011312Abstract: A semiconductor package is provided that includes a semiconductor chip that is mounted on a mount board with metal bumps interposed therebetween so as to create a gap. A structure is provided in the gap for limiting the flow of a resin, which is deposited along side the semiconductor chip, around the peripheral portion of the semiconductor chip. The structure increases the resistance to the flow of the resin in the peripheral portion of the semiconductor chip. Therefore, the rate at which the resin flows in the peripheral portion of the semiconductor chip is made lower than the rate at which the resin flows near the central portion of semiconductor chip. Accordingly, the formation of a resin-less void in the gap is suppressed so that the grade and quality of the semiconductor device is improved. In one embodiment, the structure in the gap includes projections provided on a portion of the mount board that corresponds to the peripheral portion of the semiconductor chip.Type: GrantFiled: July 29, 1997Date of Patent: January 4, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Takahito Nakazawa, Yumiko Ohshima
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Patent number: 5998243Abstract: In a method for manufacturing a flip-chip bonded semiconductor device is used an apparatus for resin-encapsulating, the apparatus which comprises a molding die consisting of a plurality of mold bodies, device for decompressing cavities of the molding die, device for heating the molding die, and device for injecting a liquid resin under pressure into the cavities, to form a resin-encapsulating layer by transfer molding. A bonded body having a semiconductor chip connected to a wiring substrate through its bumps is placed in the cavities of the molding die, the cavities are heated and decompressed, then the liquid resin is injected under pressure into the cavities through a gate to form a resin-encapsulating layer. Thus, the molding resin can be filled uniformly into the gap between the semiconductor chip and the wiring substrate in a short time to produce a flip-chip bonded semiconductor device having good performances.Type: GrantFiled: October 14, 1998Date of Patent: December 7, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Teikou Odashima, Mikio Matsui, Yoshiaki Sugizaki, Takahito Nakazawa
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Patent number: 5935375Abstract: An apparatus is provided for manufacturing a semiconductor package of the type in which a gap between a semiconductor chip and a mount board is filled with a resin. The apparatus includes resin supply means for supplying the resin along one side of the semiconductor chip, and resin supply control means for controlling the amount of resin supplied by the resin supply means such that more resin is supplied near the central portion of the semiconductor chip than near the end portions of the semiconductor chip. Also provided is a method that includes the steps of connecting the semiconductor chip and the mount board, and supplying the resin along one side of the semiconductor chip in such a manner that more resin is supplied near a central portion of the semiconductor chip than near the end portions of the semiconductor chip.Type: GrantFiled: July 29, 1997Date of Patent: August 10, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takahito Nakazawa, Hiroshi Nomura, Yumiko Ohshima
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Patent number: 5677246Abstract: In the disclosed method of manufacturing semiconductor devices with a single-sided resin-sealed package structure, when resin is filled into between the chip and the substrate, the occurrence of variations in the finishing dimensions of the package or defects in the outward appearance of the package is prevented.Type: GrantFiled: November 28, 1995Date of Patent: October 14, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Hideaki Maeta, Katsuhiko Oyama, Hiroshi Iwasaki, Yumiko Ohshima, Takahito Nakazawa