Abstract: A vehicle speed calculating device includes a vehicle speed calculating unit configured to calculate a control vehicle speed that is acquired by estimating a vehicle body speed that is a speed at which a vehicle is actually traveling, as a state variable used to control an onboard device configured to operate to realize various functions provided in the vehicle. The vehicle speed calculating unit is configured to include an extraction function of extracting at least one wheel speed acquired from at least one wheel that is assumed to be rotating in a state in which an influence causing a difference from the vehicle body speed is likely to be small, out of wheel speeds of a plurality of wheels, and a calculation function of calculating the control vehicle speed based on the at least one wheel speed extracted by the extraction function.

Abstract: According to one embodiment, a semiconductor memory device includes: a first stacked body that includes a memory region, a stepped region, and a connection region arranged in a first direction; a plurality of first pillars that is disposed in the memory region, extends in the first stacked body in the stacking direction; a plurality of second pillars that includes a second insulating layer, has a layer structure different from a layer structure of the first pillars, and extends in the stacking direction in a position overlapping a stepped portion disposed in the stepped region in the stacking direction; and a plurality of third pillars that extends in the first stacked body in the stacking direction, and has a same layer structure as the layer structure of the first pillars, at least a part of the plurality of third pillars being disposed in the connection region.

Abstract: According to one embodiment, a semiconductor memory device includes: a stacked body that includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked one by one and a stepped portion in which the plurality of conductive layers is processed in a stepped shape; and a plurality of second pillars that extends in the stacked body in the stepped portion, in which each of the plurality of second pillars includes a second insulating layer extending in the stacked body in the stacking direction, a semiconductor layer covering a side wall of the second insulating layer, a third insulating layer disposed in contact with a side wall of the semiconductor layer and covering the side wall of the semiconductor layer, and a fourth insulating layer disposed in contact with a side wall of the third insulating layer and covering the side wall of the third insulating layer.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, insulating members, first conductive layers, first pillars, and second pillars. The substrate includes a first area, a second area, block regions, and a first dummy block region. The insulating members are arranged at respective boundary portions of the block regions and the first dummy block region. The first conductive layers are partitioned by the insulating members. The first pillars penetrates the first conductive layers in a region where the first area and the block regions overlap. The second pillars penetrates at least one of the first conductive layers in a region where the first area and the first dummy block region overlap.

Abstract: A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory region in which a plurality of memory cells are disposed and a staircase region in which end portions of the plurality of conductive layers form a staircase shape. A first region of the staircase region includes a first sub-staircase portion ascending in a first direction toward the memory portion, and a second sub-staircase portion disposed side by side with the first sub-staircase portion in a second direction opposite to the first direction from the first sub-staircase portion and ascending in the second direction.

Abstract: A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory portion in which a plurality of memory cells are disposed and a staircase portion in which end portions of the plurality of conductive layers form a staircase shape. The staircase portion has three or more first sub-staircase portions ascending in a direction opposite to a direction toward the memory portion, and at least one first sub-staircase portion among the three or more first sub-staircase portions is divided into at least an upper staircase and a lower staircase by a difference in level larger than a difference in level of each stair of the first sub-staircase portion.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, insulating members, first conductive layers, first pillars, and second pillars. The substrate includes a first area, a second area, block regions, and a first dummy block region. The insulating members are arranged at respective boundary portions of the block regions and the first dummy block region. The first conductive layers are partitioned by the insulating members. The first pillars penetrates the first conductive layers in a region where the first area and the block regions overlap. The second pillars penetrates at least one of the first conductive layers in a region where the first area and the first dummy block region overlap.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, first members, first conductive layers, and first and second pillars. The substrate includes first and second areas, and block areas. The first conductive layers are split by the first members. The first pillars are provided in an area in which the first area and the block areas overlap. The second pillars are provided in an area in which the second area and the block areas overlap. The second area includes a first sub-area in which the second pillars are periodically arranged in an area that overlaps at least one block area in the block areas. In the first sub-area, at least one second pillar is omitted from the second pillars that are periodically arranged.

Abstract: A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells; and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region.

Abstract: A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory portion in which a plurality of memory cells are disposed and a staircase portion in which end portions of the plurality of conductive layers form a staircase shape. The staircase portion has three or more first sub-staircase portions ascending in a direction opposite to a direction toward the memory portion, and at least one first sub-staircase portion among the three or more first sub-staircase portions is divided into at least an upper staircase and a lower staircase by a difference in level larger than a difference in level of each stair of the first sub-staircase portion.

Abstract: An imprinting system according to an embodiment includes a first measuring device measuring an intensity of light reflected from an end of a shot area of a monitor substrate being an area on which imprinting has been performed, a dripping condition generating device generating a dripping condition of a resin-based mask material on the basis of the measured intensity of light, and an imprinting apparatus performing imprinting using the dripping condition. The imprinting apparatus includes a second measuring device measuring an intensity of light reflected from an end of a first shot area of a production substrate being an area on which imprinting has been performed, and a control unit adjusting arrangement of droplets of a resin-based mask material ejected on a second shot area of the production substrate being an area on which imprinting is to be performed on the basis of an intensity of light reflected from an end of the first shot area.

Abstract: According to an embodiment, a template includes a flat plate-shaped first member, a flat plate-shaped second member including a pattern arrangement face, and a flat plate-shaped third member provided with an opening at a position corresponding to an arrangement position of the second member. The template is dividable at a position of at least one of a first boundary between the first member and the second member and a second boundary between the first member and the third member.

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.

Abstract: A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells; and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region.

Abstract: A semiconductor memory device according to an embodiment includes, a stacked portion and a pillar. The stacked portion is provided in a first region including a memory cell and in a second region. The stacked portion includes first and second conductive layers and a first insulating layer. The first conductive layers are stacked in a first direction. The second conductive layers are stacked in the first direction above the first conductive layers. The first insulating layer is provided between an uppermost first conductive layer and a lowermost second conductive layer. The pillar penetrates the first and second conductive layers and the first insulating layer.

Abstract: Provided are a mask blank substrate processing device, a mask blank substrate processing method, a mask blank substrate fabrication method, a mask blank fabrication method, and a transfer mask fabrication method, for surface processing a mask blank substrate such that a high-level smoothness and a low-defect quality are satisfied.

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.

Abstract: An imprinting system according to an embodiment includes a first measuring device measuring an intensity of light reflected from an end of a shot area of a monitor substrate being an area on which imprinting has been performed, a dripping condition generating device generating a dripping condition of a resin-based mask material on the basis of the measured intensity of light, and an imprinting apparatus performing imprinting using the dripping condition. The imprinting apparatus includes a second measuring device measuring an intensity of light reflected from an end of a first shot area of a production substrate being an area on which imprinting has been performed, and a control unit adjusting arrangement of droplets of a resin-based mask material ejected on a second shot area of the production substrate being an area on which imprinting is to be performed on the basis of an intensity of light reflected from an end of the first shot area.

Abstract: According to one embodiment, an imprinting apparatus is provided. The imprinting apparatus includes a controller that controls a resist drop position on a wafer to be imprinted with a pattern, using a first resist drop recipe corresponding to a first topography of the wafer.

Abstract: A method for manufacturing a low-defect and high-quality mask blank substrate with minimized transfer pattern defects and high mechanical strength, particularly such that the occurrence of a phenomenon where a portion of a transfer pattern and a principal surface of the substrate therebeneath are broken off together is minimized such that there is little pattern loss. The mask blank is manufactured by preparing a mask blank substrate (X) having a substrate principal surface (X1) polished using a polishing solution containing abrasive grains, etching the substrate principal surface (X1) using catalyst-referred etching so as to remove damaged portions from the principal surface (X1), and then depositing a thin film that forms a transfer pattern on the substrate principal surface (X1) of the substrate (X) by sputtering.