Abstract: In an approach for generating a user-specific personal corpus, a processor creates a basic corpus for a first user using a first set of data sources, wherein the basic corpus includes one or more basic words and one or more vectors of the one or more basic words. A processor extracts a set of text from a second set of data sources associated with the first user. Responsive to finding an unknown word included in the set of text extracted, a processor updates the basic corpus, wherein the basic corpus is updated by replacing a vector of the unknown word with an average vector of the one or more basic words in the basic corpus created and registering the unknown word in a first personal corpus.

Abstract: Provided is a breeding apparatus that can facilitate disposition and collection of a spawning bed. A breeding apparatus includes a breeding area forming member that forms breeding areas for organisms and is open at least at the bottoms of the breeding areas, and a spawning bed sheet that forms the bottom surfaces of the breeding areas, has a belt shape, and is provided so as to be movable in a longitudinal direction of the belt shape relative to the breeding area forming member.

Abstract: An interconnect system may connect a first semiconductor device with second semiconductor device. The interconnect system includes patterned mask, conductive pads, solder bumps, and an adhesion layer. The patterned mask may be retained after it is utilized to fabricate the conductive pads and the solder bumps. The patterned mask may be thinned, and the adhesion layer may be formed upon the thinned patterned mask and upon the solder bumps. The adhesion layer and the solder bumps may be partially removed or planarized and the top surface of the adhesion layer that remains between the solder bumps may be coplanar with the top surface of the solder bumps.

Abstract: There is provided a rearing apparatus including a hatching area that holds eggs of organisms to be reared and accommodates the organisms hatched from the eggs, and a rearing area that is defined in an area larger than the hatching area at a position different from the hatching area and in which the organisms are reared. The present disclosure provides a rearing apparatus that can implement high-density and large-scale rearing by effectively utilizing areas.

Abstract: An interconnected semicondcutor subassembly structure and formation thereof. The interconnected semicondcutor subassembly structure includes an interconnect structure, and first and second semicondcutor dies bonded to respective portions of a top surface of the interconnect structure. The interconnected semicondcutor subassembly structure further includes an underfill layer formed within a first gap located between a bottom surface of the first semiconductor die and the first portion the top surface of the interconnect structure, formed within a second gap located between the bottom surface of the second semiconductor die and the second portion of the top surface of the interconnect structure, and formed within a first portion of a third gap located between the first semicondcutor die and the second semicondcutor die. A top surface of the underfill layer formed within the first portion of the third gap located between the first and second semicondcutor dies has a concave meniscus shape.

Abstract: An interconnected semiconductor subassembly structure includes an interconnect structure; a first semiconductor die bonded to a first portion of a top surface of the interconnect structure; a second semiconductor die bonded to a second portion of the top surface of the interconnect structure; and a resin layer located within at least a first portion of a gap between the first semiconductor die and the second semiconductor die, wherein at least one of a top surface and a bottom surface of the resin layer located within the at least first portion of the gap has a concave meniscus shape.

Abstract: Interconnecting a first chip and a second chip includes mounting the first and second chips to a chip handler having an opening and at least one support surface. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The first surface of the first chip and the first surface of the second chip mounted to the chip handler are supported by the at least one support surface of the chip handler. The first and second chips are placed on a chip support member with the chip handler from the second surfaces. A bridge member is inserted by a bridge handler through the opening of the chip handler to place the bridge member onto the first sets of terminals of the first and second chips that are exposed from the opening.

Abstract: An integrated circuit package includes a substrate including at least one electrical connection to at least one of power or ground. The package further includes a bridge structure including at least one layer of conductive material and at least one layer of insulative material. The bridge structure is configured to be coupled to the substrate such that the conductive material is electrically connected to the at least one electrical connection. The bridge structure includes a side pad made of conductive material that is electrically connected to the at least one electrical connection. The side pad is in direct contact with the conductive material and with the insulative material of the bridge structure. The side pad forms an end face of the bridge structure such that the conductive material of the side pad is exposed.

Abstract: Interconnecting a first chip and a second chip by a bridge member includes a chip handler for handling the first chip and the second chip. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The chip handler has an opening and at least one support surface for supporting the first surfaces of the first chip and the second chip when the first chip and the second chip are mounted to the chip handler. A chip support member supports the first chip and the second chip from the second surfaces, and a bridge handler is provided for inserting the bridge member through the opening of the chip handler and for placing the bridge member onto the first sets of terminals of the first chip and the second chip.

Abstract: An X-ray Computed Tomography (CT) apparatus according to an embodiment includes a gantry. The gantry includes: a rotating base rotatably supported; a plurality of units fixed to the rotating base; and a fixing member that is separately provided, is positioned apart from the rotating base, and is configured to fix at least two of the plurality of units with each other.

Abstract: A technique relating to a battery structure is disclosed. Abase substrate and a battery layer having a support substrate are prepared. The battery layer includes a protection layer formed on the support substrate, a film battery element formed on the protection layer and an insulator covering the film battery element. The battery layer is placed onto the base substrate with the bottom of the support substrate facing up. The support substrate is then removed from the battery layer at least in part by etching while protecting the film battery element by the protection layer. A stacked battery structure including the base substrate and the two or more battery layers is also disclosed.

Abstract: Embodiments are disclosed for a method for restoring a wearable biological sensor. The method includes determining that a wearable biological marker sensor comprising a reference electrode is placed within a restoration apparatus. The restoration apparatus includes a correct reference electrode, a counter electrode, and a chloride solution. The reference electrode is in electrical contact with the correct reference electrode and the counter electrode through the chloride solution. The method additionally includes determining whether the reference electrode is degraded based on a voltage differential between the reference electrode and the correct reference electrode. The method also includes restoring the reference electrode, if the reference electrode is degraded, by applying a voltage to a circuit. The circuit includes the reference electrode and the counter electrode. Further, multiple chloride ions of the chloride solution bond with a plurality of silver atoms of the reference electrode.

Abstract: A technique relating to a battery structure is disclosed. A base substrate and a battery layer having a support substrate are prepared. The battery layer includes a protection layer formed on the support substrate, a film battery element formed on the protection layer and an insulator covering the film battery element. The battery layer is placed onto the base substrate with the bottom of the support substrate facing up. The support substrate is then removed from the battery layer at least in part by etching while protecting the film battery element by the protection layer. A stacked battery structure including the base substrate and the two or more battery layers is also disclosed.

Abstract: There is provided a rearing apparatus for rearing an organism includes: a box-shaped rearing case; at least one perching member that is held in the rearing case and that is capable of perching the organism; and a separating member that is provided in the rearing case and that is movable along the perching member. The separating member is configured to separate the organism perched at the perching member from the perching member by the separating member moving along the perching member.

Abstract: Aspects of the present disclosure relate to a method for fabricating an interconnection layer carrying structure. A carrier is provided. An organic layer is deposited on the carrier, wherein the organic layer includes a multi-layer wiring structure therein, and the uppermost surface is covered with an organic top layer. A sacrificial layer is deposited on the organic top layer. The carrier and the organic layer are diced together with the sacrificial layer.

Abstract: Interconnecting a first chip and a second chip by a bridge member includes a chip handler for handling the first chip and the second chip. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The chip handler has an opening and at least one support surface for supporting the first surfaces of the first chip and the second chip when the first chip and the second chip are mounted to the chip handler. A chip support member supports the first chip and the second chip from the second surfaces, and a bridge handler is provided for inserting the bridge member through the opening of the chip handler and for placing the bridge member onto the first sets of terminals of the first chip and the second chip.

Abstract: An integrated circuit package includes a substrate including at least one electrical connection to at least one of power or ground. The package further includes a bridge structure including at least one layer of conductive material and at least one layer of insulative material. The bridge structure is configured to be coupled to the substrate such that the conductive material is electrically connected to the at least one electrical connection. The bridge structure includes a side pad made of conductive material that is electrically connected to the at least one electrical connection. The side pad is in direct contact with the conductive material and with the insulative material of the bridge structure. The side pad forms an end face of the bridge structure such that the conductive material of the side pad is exposed.

Abstract: Aspects of the present disclosure relate to a method for fabricating an interconnection layer carrying structure. A carrier is provided. An organic layer is deposited on the carrier, wherein the organic layer includes a multi-layer wiring structure therein, and the uppermost surface is covered with an organic top layer. A sacrificial layer is deposited on the organic top layer. The carrier and the organic layer are diced together with the sacrificial layer.

Abstract: A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher. The surface treatment includes sandblasting.

Abstract: An interconnection structure is disclosed. The interconnection structure includes a base substrate, a set of conductive pads disposed on the base substrate and an interconnection layer disposed on the base substrate. The interconnection layer has an edge located next to the set of the conductive pads and includes a set of side connection pads located and disposed at the edge of the interconnection layer. Each side connection pad is arranged with respect to a corresponding one of the conductive pads disposed on the base substrate.