Abstract: A method of forming stacked capacitors over first field effect transistors having been provided in a memory cell area of a semiconductor memory device and at least a second field effect transistor in a peripheral circuit area of the semiconductor memory device. A first insulation film is entirely formed which extends over first gate electrodes of the first field effect transistors and within first apertures defined between the first gate electrodes as well as a second gate electrode of the second field effect transistor. A first inter-layer insulator is entirely formed which extends over the first insulation film. A surface of the first inter-layer insulator is planarized. A first contact hole is formed in the first insulation film. A first conductive film is entirely formed over the first planarized surface of the first inter-layer insulator and within the first contact hole.

Abstract: A semiconductor memory device including memory cells with the stacked-capacitor structure that makes it possible to prevent a contact pad from being damaged. This device includes a memory cell area and a peripheral circuit area formed on a semiconductor substrate. An interlayer insulating layer having first and second penetrating holes is formed to cover the entire substrate. A capacitor has lower and upper electrode and a dielectric located between these electrodes. The lower electrode is electrically connected to the first element through the first penetrating hole. Each of the peripheral circuits has a second element, a contact pad electrically connected to the second element, a pad insulating layer formed to cover the contact pad, a pad protection layer formed on the pad insulating layer, and an interconnection conductor electrically connected to the contact pad through a contact hole penetrating the pad protection and pad insulating layers.

Abstract: A semiconductor dynamic random access memory device has a switching transistor fabricated on a first area of a silicon substrate, another switching transistor fabricated on a second area of the silicon substrate and forming a part of a peripheral circuit, a first inter-level insulating structure covering the first and second switching transistors, a bit line formed on the first inter-level insulating structure and electrically connected to the drain region of the first switching transistor, a signal wiring layer formed on the first inter-level insulating structure and electrically connected to the drain region of the second switching transistor, a second inter-level insulating layer covering the bit line and the signal wiring layer and a storage capacitor formed on the second inter-level insulating layer and electrically connected to the drain region of the second switching transistor; parasitic capacitance is the major factor for the signal propagating speed along the bit line, and resistance is the major fa

Abstract: A semiconductor memory device including memory cells with the stacked-capacitor structure that makes it possible to prevent a contact pad from being damaged. This device includes a memory cell area and a peripheral circuit area formed on a semiconductor substrate. An interlayer insulating layer having first and second penetrating holes is formed to cover the entire substrate. A capacitor has lower and upper electrode and a dielectric located between these electrodes. The lower electrode is electrically connected to the first element through the first penetrating hole. Each of the peripheral circuits has a second element, a contact pad electrically connected to the second element, a pad insulating layer formed to cover the contact pad, a pad protection layer formed on the pad insulating layer, and an interconnection conductor electrically connected to the contact pad through a contact hole penetrating the pad protection and pad insulating layers.

Abstract: A semiconductor memory device including memory cells with the stacked-capacitor structure that makes it possible to prevent a contact pad from being damaged. This device includes a memory cell area and a peripheral circuit area formed on a semiconductor substrate. An interlayer insulating layer having first and second penetrating holes is formed to cover the entire substrate. A capacitor has lower and upper electrode and a dielectric located between these electrodes. The lower electrode is electrically connected to the first element through the first penetrating hole. Each of the peripheral circuits has a second element, a contact pad electrically connected to the second element, a pad insulating layer formed to cover the contact pad, a pad protection layer formed on the pad insulating layer, and an interconnection conductor electrically connected to the contact pad through a contact hole penetrating the pad protection and pad insulating layers.

Abstract: A semiconductor dynamic random access memory device has a memory cell array fabricated on a silicon-on-insulator region and peripheral and interface circuits fabricated on a bulk region; even if the circuit components of the peripheral circuit are increased together with the memory cells, the bulk region effectively radiates the heat generated by the peripheral and interface circuits, thereby preventing the memory cells from a temperature rise.

Abstract: After formation of a node-contact hole through an interlayer insulation film, an LPCVD using a monosilane gas is employed to form a non-doped polycrystalline silicon film on the interlayer insulation film, filling the node-contact hole. The non-doped polycrystalline silicon film is converted into an n-type polycrystalline silicon film. Using a disilane gas and a phosphine gas as raw gases, an n-type doped amorphous silicon film is formed. After patterning, a heat treatment is employed under a super-high vacuum pressure to convert the n-type doped amorphous silicon film into an n-type polycrystalline silicon film with a rugged surface. A capacitive element is fabricated with a reduced dispersion of capacitance in a simplified manner suitable for a miniaturization of cell size.

Abstract: A method which can markedly improve the flatness of a semiconductor integrated circuit device by forming selectively a layer insulating film on an underlying substrate having level differences is disclosed. First, a Ti--W alloy film is formed on a member which brings about level differences due to wirings or the like, then a PECVD silicon oxide film is formed followed by a plasma treatment using CF.sub.4 gas. Further, a silicon oxide film is deposited by atmospheric pressure CVD using ozone and tetraethoxysilane. Then, the surface is flattened by etchback using an organic SOG film, and a silicon oxide film is formed by plasma excited CVD.

Abstract: A DRAM with improved stacked-capacitor memory cells is provided. In each memory cell, an aluminum wiring line acting as a part of one of word lines is covered with a interlayer insulator film, and on the interlayer insulator film, a storage capacitor is formed. A storage electrode of the capacitor is contacted with a source/drain region of an MOS select transistor through a contact hole in the interlayer insulator film. The wiring line is not required to be formed over the capacitor and as a result, thickness of the storage electrode of the capacitor is not limited by a fabrication condition. Thus, a dielectric such as Ta.sub.2 O.sub.5 with a larger dielectric constant can be employed as the capacitor dielectric, so that the memory cell area can be reduced.

Abstract: A process for fabricating a semiconductor device having a capacitor is disclosed.

Abstract: A semiconductor memory device having a cell structure capable of maintaining a capacitance of a stacked capacitor at a satisfactory level, which is characterized in that in the first aspect, an insulation layer of an oxide film is formed on an upper surface of a polysilicon gate electrode and a side-wall of an oxide film is formed on the side surface thereof, and in the second aspect, after opening a storage electrode contact, another side-wall of an oxide film Is formed thereon. Accordingly, the space between the storage electrode contact and the polysilicon gate electrode can be made zero (0), that is, in a self-alignment form, resulting in a reduction in the necessary planar surface area of a memory cell to about 5 .mu.m.sup.2 or less.

Abstract: An impurity doped region is formed in a semiconductor substrate, and an insulating layer is formed thereon. A conductive layer is formed and is patterned by a photolithography process Then, a conductive sidewall is formed inside of the conductive layer. The insulating layer is etched with a mask of the conductive sidewall and the conductive layer to create a contact hole leading to the impurity doped region. A capacitor lower electrode layer is deposited within the contact hole. Thus, a capacitor insulating layer and a capacitor upper electrode layer are formed, to obtain a stacked capacitor.

Abstract: In a semiconductor random access memory device of the type having two or more data lines arranged in association with a single data input or output terminal is provided a memory testing circuit which is characterized in that test data is supplied to every one of the data lines and is written all at a time into a plurality of memory cells which may include those located adjacent each other, wherein the number of the memory cells into which test data is to be written simultaneously depends on the data lines to be selected so that different pieces of data can be respectively written into the individual memory cells.