Patents by Inventor Takaichi Hirata

Takaichi Hirata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7897969
    Abstract: A solid-state image pickup device includes a pixel array area in which pixels each including a photoelectric conversion element are two-dimensionally arranged; first control means for performing control such that signals of pixels in a desired region of the pixel array area are sequentially read row by row; and second control means for performing control such that, when the signals of the pixels in the desired region are sequentially read row by row by the first control means, pixels in particular regions below and above the desired region are sequentially reset row by row.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: March 1, 2011
    Assignee: Sony Corporation
    Inventors: Yoshinori Muramatsu, Takahiro Abiru, Takaichi Hirata
  • Publication number: 20060237721
    Abstract: A solid-state image pickup device includes a pixel array area in which pixels each including a photoelectric conversion element are two-dimensionally arranged; first control means for performing control such that signals of pixels in a desired region of the pixel array area are sequentially read row by row; and second control means for performing control such that, when the signals of the pixels in the desired region are sequentially read row by row by the first control means, pixels in particular regions below and above the desired region are sequentially reset row by row.
    Type: Application
    Filed: April 18, 2006
    Publication date: October 26, 2006
    Inventors: Yoshinori Muramatsu, Takahiro Abiru, Takaichi Hirata
  • Patent number: 7123067
    Abstract: In a charge-pump booster circuit, the control clock is controlled on a small-step basis to thereby suppress the boost amplitude and the occurrence of various noises. Provided are a charge-pump booster circuit section for boosting an external power voltage in absolute value level, a boost-voltage feedback section for controlling the booster circuit section, and a clock buffer section. In the boost-voltage feedback section, an output level of the booster circuit section is detected by a voltage detecting section. This is compared with a reference level, and depending upon the comparison result, a count operation is made in an up/down counter section. Based on the count value, the control amount is shifted on a small-step basis from the D/A converter section, thereby controlling the power voltage of the clock buffer section 300 through the level shifter section.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: October 17, 2006
    Assignee: Sony Corporation
    Inventors: Yukihiro Yasui, Takaichi Hirata, Tsutomu Haruta
  • Publication number: 20040017247
    Abstract: In a charge-pump booster circuit, the control clock is controlled on a small-step basis to thereby suppress the boost amplitude and the occurrence of various noises. Provided are a charge-pump booster circuit section for boosting an external power voltage in absolute value level, a boost-voltage feedback section for controlling the booster circuit section, and a clock buffer section. In the boost-voltage feedback section, an output level of booster circuit section is detected by a voltage detecting section. This is compared with a reference level, and depending upon the comparison result, count operation is made in an up/down counter section. Based on the count value, control amount is shifted on a small-step basis from the D/A converter section, thereby controlling the power voltage of the clock buffer section 300 through the level shifter section.
    Type: Application
    Filed: May 23, 2003
    Publication date: January 29, 2004
    Inventors: Yukihiro Yasui, Takaichi Hirata, Tsutomu Haruta