Patents by Inventor Takaji Ishikawa

Takaji Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8134381
    Abstract: A probe card is provided which includes: probe needles electrically contacting input/output terminals of an IC device formed on a semiconductor wafer W; a mount base on which the probe needles are mounted; a support column supporting the mount base, a circuit board having interconnect patterns electrically connected to the probe needles via bonding wires; and a base member and stiffener for reinforcing the probe card. The mount base and the circuit board are noncontact.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: March 13, 2012
    Assignee: Advantest Corporation
    Inventors: Yoshihiro Abe, Takaji Ishikawa, Noriaki Shimasaki, Shigeru Matsumura
  • Publication number: 20100102837
    Abstract: A probe card is provided which includes: probe needles electrically contacting input/output terminals of an IC device formed on a semiconductor wafer W; a mount base on which the probe needles are mounted; a support column supporting the mount base, a circuit board having interconnect patterns electrically connected to the probe needles via bonding wires; and a base member and stiffener for reinforcing the probe card. The mount base and the circuit board are noncontact.
    Type: Application
    Filed: March 18, 2008
    Publication date: April 29, 2010
    Applicant: ADVANTEST CORPORATION
    Inventors: Yoshihiro Abe, Takaji Ishikawa, Noriaki Shimasaki, Shigeru Matsumura
  • Patent number: 7667471
    Abstract: A contact pin (50) for contacting a terminal of a wafer and supplying a signal to that wafer is provided with a first conductive layer (51b) composed of a first conductive material having a relatively higher hardness than the oxide film formed on the terminal of the wafer, a second conductive layer (51c) composed of a second conductive material having a relatively lower hardness than the oxide film, and a base material (51a) with the first conductive layer (51b) and second conductive layer (51c) formed at the outside, the first conductive layer (51b) being formed so as to closely contact the outside of the second conductive layer (51c), the first conductive layer (51b) and second conductive layer (51c) both being exposed at the front end face (50a) of the contact pin (50).
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: February 23, 2010
    Assignee: Advantest Corporation
    Inventors: Fumio Kurotori, Takaji Ishikawa, Tadao Saito
  • Patent number: 7484285
    Abstract: A system for mating and demating a plurality of connectors mounted on a socket board with and from a plurality of corresponding connectors mounted on a motherboard includes: an adapter that is arranged above a surface opposite to the socket board surface on which the connectors are arranged and is movable in a direction in which the connectors are mated and demated; pressing means which contacts the surface of the socket board on which the semiconductor components are placed to press the socket board to the motherboard by lowering the adapter; and pulling means each of which engages with an engaging hole formed in the socket board and pulls the socket board in the direction in which the socket board is separated from the motherboard by lifting the adapter.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: February 3, 2009
    Assignee: Advantest Corp.
    Inventors: Masanori Kaneko, Hiroyuki Hama, Takaji Ishikawa, Shigeru Matsumura
  • Patent number: 7482821
    Abstract: A probe card 1 is composed of a plurality of probe pins 50 having wafer-side plungers51 at one end portion and substrate-side plungers52 on the other end side; two probe guides 30 and 40 one above the other for supporting the plurality of probe pins 50, so that the plurality of probe pins 50 are arranged to be corresponding to an arrangement of external terminals of a semiconductor wafer and the wafer-side plungers 51 of the probe pins 50 protrude; a print substrate 10 having pads 13 for the substrate-side plungers 52 of the probe pins 50 supported by the probe guides 30 and 40 to contact; and a stiffener 20 provided on the back surface of the print substrate 10.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: January 27, 2009
    Assignee: Advantest Corporation
    Inventors: Takaji Ishikawa, Fumio Kurotori, Tadao Saito
  • Publication number: 20080143366
    Abstract: A contact pin (50) for contacting a terminal of a wafer and supplying a signal to that wafer is provided with a first conductive layer (51b) composed of a first conductive material having a relatively higher hardness than the oxide film formed on the terminal of the wafer, a second conductive layer (51c) composed of a second conductive material having a relatively lower hardness than the oxide film, and a base material (51a) with the first conductive layer (51b) and second conductive layer (51c) formed at the outside, the first conductive layer (51b) being formed so as to closely contact the outside of the second conductive layer (51c), the first conductive layer (51b) and second conductive layer (51c) both being exposed at the front end face (50a) of the contact pin (50).
    Type: Application
    Filed: December 14, 2004
    Publication date: June 19, 2008
    Inventors: Fumio Kurotori, Takaji Ishikawa, Tadao Saito
  • Publication number: 20050280428
    Abstract: A probe card 1 is composed of a plurality of probe pins 50 having wafer-side plungers 51 at one end portion and substrate-side plungers 52 on the other end side; two probe guides 30 and 40 one above the other for supporting the plurality of probe pins 50, so that the plurality of probe pins 50 are arranged to be corresponding to an arrangement of external terminals of a semiconductor wafer and the wafer-side plungers 51 of the probe pins 50 protrude; a print substrate 10 having pads 13 for the substrate-side plungers 52 of the probe pins 50 supported by the probe guides 30 and 40 to contact; and a stiffener 20 provided on the back surface of the print substrate 10. The probe guides 30 and 40 are produced by a material having substantially the same thermal expansion coefficient as that of the semiconductor wafer, and fixed to the print substrate 10 and the stiffener 20 at the circumferential portion and the center portion.
    Type: Application
    Filed: June 14, 2005
    Publication date: December 22, 2005
    Inventors: Takaji Ishikawa, Fumio Kurotori, Tadao Saito
  • Patent number: 6932635
    Abstract: To control the temperature of an electronic component testing socket without mixing any noise into a test signal to be applied to an electronic component and a respond signal to be read from the electronic component when conducting a test on the electronic component, a first space 67 in the electronic component testing socket base 6 and a socket body inside space 75 in the electronic component testing socket 7 are connected via a gas outlet 65 and a gas inlet 76, and a second space 68 in the electronic component testing socket base 6 and a socket body inside space 75 in the electronic component testing socket 7 are connected via a gas inlet 66 and a gas outlet 77.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: August 23, 2005
    Assignee: Advantest Corporation
    Inventors: Takaji Ishikawa, Hiroto Nakamura
  • Publication number: 20050081372
    Abstract: Even when many connectors are provided, all the connectors are easily and surely mated and demated at the same time.
    Type: Application
    Filed: February 25, 2003
    Publication date: April 21, 2005
    Inventors: Masanori Kaneko, Hiroyuki Hama, Takaji Ishikawa, Shigeru Matsumura
  • Publication number: 20040077200
    Abstract: To control the temperature of an electronic component testing socket without mixing any noise into a test signal to be applied to an electronic component and a respond signal to be read from the electronic component when conducting a test on the electronic component, a first space 67 in the electronic component testing socket base 6 and a socket body inside space 75 in the electronic component testing socket 7 are connected via a gas outlet 65 and a gas inlet 76, and a second space 68 in the electronic component testing socket base 6 and a socket body inside space 75 in the electronic component testing socket 7 are connected via a gas inlet 66 and a gas outlet 77.
    Type: Application
    Filed: June 6, 2003
    Publication date: April 22, 2004
    Inventors: Takaji Ishikawa, Hiroto Nakamura