Patents by Inventor Takaji Takenaka

Takaji Takenaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6272020
    Abstract: A semiconductor device-mounting substrate is provided with a semiconductor device, a capacitor device, and a wiring substrate. The wiring substrate has a space in which the capacitor device should be located, and the capacitor device is locate in the space. Terminals of a driving power supply wiring for the semiconductor device are provided on a surface of the space, and the terminals are connected with the capacitor device.
    Type: Grant
    Filed: October 15, 1998
    Date of Patent: August 7, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hiromi Tosaki, Takaji Takenaka, Kazutoshi Takahashi, Norio Sengoku, Toshitada Netsu
  • Patent number: 5291419
    Abstract: A method for evaluating the life of a connection between members including the steps of extracting parameters defining the shearing strain of a predetermined model representing the connection thereby to calculate the values of plural shearing strains of the connection, calculating the equivalent strain amplitude corresponding to thermal fatigue stress for each of the values of the plural shearing strains defining the relationship between the shearing strain and the equivalent strain amplitude, formulating a life evaluation criterion equation expressed using the equivalent strain amplitude, calculating, for the connection, the equivalent strain amplitude corresponding to each of the shearing strains actually measured using the equation, and substituting the equivalent strain amplitude for the life evaluation criterion equation to acquire the life of the connection.
    Type: Grant
    Filed: January 6, 1992
    Date of Patent: March 1, 1994
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Ryohei Satoh, Katsuhiro Arakawa, Kiyoshi Kanai, Tsutomu Takahashi, Takaji Takenaka, Haruhiko Imada
  • Patent number: 5257452
    Abstract: A through hole is formed by a drill in a defective through hole in a board. An insulating resin is coated on the inner surface of the through hole and a cylindrical conductor is closely fixed with an adhesive to the hole h1 to form a reproduced through hole. Thereafter, as usual, a part lead is inserted into and soldered in the reproduced through hole to thereby recover the connection of the lead with the wiring circuit copper foil impaired by the recovering operation of the defective through hole using an external lead.
    Type: Grant
    Filed: May 21, 1992
    Date of Patent: November 2, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Imai, Takashi Itoh, Takaji Takenaka
  • Patent number: 5249100
    Abstract: Disclosed is an electronic circuit device in which the solder (14) connecting lead pins (6) to the ceramic substrate (2) has a melting point of C. to C. and has a tensile strength being low in such an extent that a thermal contraction stress generated in a cooling process of the solder (14) from the melting point thereof is low and the substrate (2) does not break. The solder (14) is a Au-Ge alloy containing 10-15 wt % of Ge. Electronic circuit devices, which employ the above solder (14) in the connections, are free from damages in the ceramic wiring substrate (2) due to the bonding. Further, when the electronic circuit device undergoes a series of assembly processes after the above bonding, such solder (14) does not melt, and wettability of such solder (14) is favorable.
    Type: Grant
    Filed: May 11, 1990
    Date of Patent: September 28, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Ryohei Satoh, Kazuo Hirota, Takaji Takenaka, Hideki Watanabe, Toshinori Ameya, Toshihiko Ohta
  • Patent number: 5136360
    Abstract: An electronic circuit device comprising an electronic part having a gold-plated connecting terminal arranged thereon connected through a solder to a circuit substrate on the predetermined connecting element thereof, in which the connecting terminal of the electronic part and the solder-connected portion of the circuit substrate are constituted by an alloy composition consisting of 1.0 to 8.0 wt. % of Ag, 0.1 to 6.0 wt % of Au and the balance of Sn, is provided. The device is made by using a solder for use in connecting a gold-plated connecting terminal which consists of 1.0 to 8.
    Type: Grant
    Filed: August 6, 1990
    Date of Patent: August 4, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Masahide Harada, Ryohei Satoh, Fumiyuki Kobayashi, Takaji Takenaka, Toshitada Netsu, Hideaki Sasaki, Mitugu Shirai
  • Patent number: 4930002
    Abstract: In a pin grid array type multi-chip module structure comprised of a ceramic multi-layer wiring board having the top surface on which a plurality of semiconductor devices are carried, divisional board areas each having the same size are respectively allotted to individual semiconductor devices of the same type. Within respective divisional board areas, the positional relation between the array arrangement of connecting pads on the top surface for connection to the semiconductor devices and the array arrangement of I/O pins on the bottom surface of the board is so determined as to be constant. Metallized patterns inside the board which are to be connected power supply I/O pins and ground I/O pins are made constant for respective divisional board areas allotted to individual semiconductor devices of the same type.
    Type: Grant
    Filed: March 22, 1988
    Date of Patent: May 29, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Takaji Takenaka, Tositada Netsu, Hidetaka Shigi, Masakazu Yamamoto
  • Patent number: 4836434
    Abstract: An airtight packaging apparatus for covering with a cap a multichip module having LSI chips mounted on a ceramic substrate and for sealing the cap and substrate by means of solder includes a receptacle for accommodating the multichip module, valves for supplying gas to the receptacle and exhausting the receptacle, a retainer for holding the cap and adjusting the positional relation with respect to the multichip module, and a heater for heating solder of the junction between the multichip module and the cap. After solder has been heated and melted, the multichip module and the cap are sealed to each other.
    Type: Grant
    Filed: May 30, 1986
    Date of Patent: June 6, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Takaji Takenaka, Hideki Watanabe, Fumiyuki Kobayashi
  • Patent number: 4725925
    Abstract: A circuit board including resistors on one surface of a board or substrate having through hole conductors arranged in a lattice like fashion. At least one electrode is formed on a surface of the resistors, at least one electrode being formed by removing a portion of a surface of the board or substrate coaxially with the through hole conductors thereby forming substantially disk-shaped resistors.
    Type: Grant
    Filed: December 24, 1984
    Date of Patent: February 16, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Tanaka, Kazuo Hirota, Akira Murata, Fumiuki Kobayashi, Takaji Takenaka
  • Patent number: 4706165
    Abstract: In a multilayer circuit board wherein a plurality of electronic parts are provided on a first principal plane, a plurality of brazing pads for pins are respectively arranged on a second principal plane and a plurality of wiring layers having wiring nets for connecting said electrical parts are formed between these principal planes. The EC pads for I/O leads for connecting discrete wires is provided to said first principal plane. EC pads are provided on said second principal plane and are connected to the brazing pads for pins in such a manner as to be electrically separable as required. The EC pads for I/O leads and the brazing pads for pins are connected through the interior of the multilayer circuit board and the EC pads are connected to the wiring net through the interior of the multilayer circuit board.
    Type: Grant
    Filed: October 15, 1986
    Date of Patent: November 10, 1987
    Assignees: Hitachi Microcomputer Engineering Co., Ltd., Hitachi, Ltd.
    Inventors: Takaji Takenaka, Hideki Watanabe, Haruhiko Imada
  • Patent number: 4619316
    Abstract: In an apparatus wherein heat generating bodies such as integrated circuit chips are cooled by utilizing boiling of a liquid; a heat transfer apparatus characterized in that a heat conductive member which has a plurality of layers of cavity groups and apertures for bringing the cavity groups into communication is installed on a surface of each of the heat generating bodies.
    Type: Grant
    Filed: April 24, 1985
    Date of Patent: October 28, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Wataru Nakayama, Tadakatsu Nakajima, Shigeki Hirasawa, Akiomi Kohno, Takaji Takenaka