Abstract: A method of manufacturing a semiconductor device include a step of forming an insulating layer, which is obtained by building up a first oxide film, a nitride film and a second oxide film on a substrate in the order mentioned, and a Salicide step of forming a Salicide-structure gate electrode on the insulating film. A silicidation reaction between the substrate surface and an N+ diffusion region is prevented in the Salicide step by causing the insulating layer to remain even in a region on the substrate besides that immediately underlying the gate electrode.

Abstract: Disclosed is a device and a method for enabling a programmable semiconductor memory device to provide a block selection transistor of a high voltage withstand type, to prevent the voltage from being decreased at the time of programming, to prevent the readout current from being decreased and to provide a constant sum resistance of the electrically conductive regions without dependency upon the memory cell locations.

Abstract: A method of manufacturing a semiconductor device include a step of forming an insulating layer, which is obtained by building up a first oxide film, a nitride film and a second oxide film on a substrate in the order mentioned, and a Salicide step of forming a Salicide-structure gate electrode on the insulating film. A silicidation reaction between the substrate surface and an N+ diffusion region is prevented in the Salicide step by causing the insulating layer to remain even in a region on the substrate besides that immediately underlying the gate electrode.

Abstract: Disclosed are device and method for enabling a programmable semiconductor memory device to provide a block selection transistor of a high voltage withstand type, to prevent the voltage from being decreased at the time of programming and to prevent the readout current from being decreased and to provide a constant sum resistance of the electrically conductive regions without dependency upon the memory cell locations. In a pair of two electrically conductive regions, provided for extending parallel to and in separation from each other on a substrate surface, one longitudinal end of one of the electrically conductive regions is diagonally connected to the other longitudinal end of the other electrically conductive region by a wiring to form a set of sub bit lines. On both ends of the memory cell array, there are provided selection transistors for interconnecting the sub bit lines and main bit lines.

Abstract: A method is provided for wiring semiconductor integrated circuits which produces a shielding effect while increasing the wiring area to a small extent. On one side of each of a plurality signal wires, a shielding wire made of the same material and having the same length as the signal wire is provided. The shielding wires are set to the ground potential via aluminum wiring extended from GND pads. Shielding wire segments are separated by cranking points.

Abstract: A semiconductor memory device includes a memory cell matrix section, a reference memory cell matrix section and a sensing circuit. The memory cell matrix section includes memory cells arranged in a first matrix. When one of the memory cells is selected based on an address signal, a read data signal corresponding to a storage data of the selected memory cell is outputted. The reference memory cell matrix section includes reference memory cells arranged in a second matrix, and outputs a reference data signal for the read data signal from the selected memory cell. The sensing circuit senses the storage data based on the read data signal from the memory cell matrix section and the reference data signal from the reference memory cell matrix section. At this time, the reference memory cell matrix section outputs the reference data signal to the sensing circuit such that the reference data signal appears in substantially synchronous with the data read signal.

Abstract: A semiconductor memory device is provided with a memory cell array, a sense circuit which activates main bit lines in the memory cell array, a buffer which generates an activating signal which activates the sense circuit from a control signal, an address designating section which selects a memory cell indicated by an address signal among a plurality of memory cells in the memory cell array, and a delay circuit which delays the activating signal and outputting it to the sense circuit. The address designating section activates a word line to which a memory cell indicated by the address signal is connected after some delay from the activation of a chip enable signal.

Abstract: A semiconductor memory device is provided with a memory cell array, a sense circuit which activates main bit lines in the memory cell array, a buffer which generates an activating signal which activates the sense circuit from a control signal, an address designating section which selects a memory cell indicated by an address signal among a plurality of memory cells in the memory cell array, and a delay circuit which delays the activating signal and outputting it to the sense circuit. The address designating section activates a word line to which a memory cell indicated by the address signal is connected after some delay from the activation of a chip enable signal.

Abstract: A method is provided for wiring semiconductor integrated circuits which produces a shielding effect while increasing the wiring area to a small extent.

Abstract: A semiconductor memory device includes a memory cell matrix section, a reference memory cell matrix section and a sensing circuit. The memory cell matrix section includes memory cells arranged in a first matrix. When one of the memory cells is selected based on an address signal, a read data signal corresponding to a storage data of the selected memory cell is outputted. The reference memory cell matrix section includes reference memory cells arranged in a second matrix, and outputs a reference data signal for the read data signal from the selected memory cell. The sensing circuit senses the storage data based on the read data signal from the memory cell matrix section and the reference data signal from the reference memory cell matrix section. At this time, the reference memory cell matrix section outputs the reference data signal to the sensing circuit such that the reference data signal appears in substantially synchronous with the data read signal.

Abstract: A semiconductor memory device includes a memory cell matrix section, a reference memory cell matrix section and a sensing circuit. The memory cell matrix section includes memory cells arranged in a first matrix. When one of the memory cells is selected based on an address signal, a read data signal corresponding to a storage data of the selected memory cell is outputted. The reference memory cell matrix section includes reference memory cells arranged in a second matrix, and outputs a reference data signal for the read data signal from the selected memory cell. The sensing circuit senses the storage data based on the read data signal from the memory cell matrix section and the reference data signal from the reference memory cell matrix section. At this time, the reference memory cell matrix section outputs the reference data signal to the sensing circuit such that the reference data signal appears in substantially synchronous with the data read signal.

Abstract: A semiconductor memory device comprises matrix memory cell banks, a reference cell bank device, and a sense circuit. The matrix memory cell banks and the reference cell bank device have deputy bit lines which are implemented by embedded diffused layers, respectively. Each of the matrix memory cell banks comprises a first set of memory cells. The first set of memory cells are for holding data. The reference cell bank device comprises a predetermined number of reference cell banks which are directly connected. Each of the reference cell banks comprises a second set of reference cells. The reference cells are for holding reference voltages. The sense circuit receives data voltages which are read out from the matrix memory cell banks and the reference voltages from the reference cell bank device to determine levels of the data voltages by comparing the data voltages with the reference voltages.

Abstract: A semiconductor memory device includes a memory cell array composed of a plurality of memory cells arranged in a matrix manner and at least one reference memory cell, wherein a plurality of digit lines are respectively connected to columns of memory cells, a plurality of word lines are respectively connected to rows of memory cells, and a reference digit line is connected to the reference memory cell, an address circuit for selecting one of the plurality of digit lines and one of the plurality of word lines in response to input of an address to select one of the plurality of memory cells, a sense amplifier connected to the plurality of digit lines and the reference digit line, for sensing data which has been stored in the selected memory cell in response to a first portion of a sense control signal, a discharging circuit for discharging charge of at least one of the plurality of digit lines which is connected to the selected memory cell and charge of the reference digit line in response to a second portion of

Abstract: In a semiconductor memory device including ROM cells, a digit line for receiving read data from a selected one of the at the memory cells, and a bias circuit for amplifying a voltage at the digit line, a differential amplifier, which has a positive phase input, a negative phase input, a positive phase output and a negative phase output, is provided. The positive phase input is connected to the output of the bias circuit. The negative phase output is connected to the negative phase input, thereby establishing a positive feedback loop in the differential amplifier.

Abstract: A semiconductor device includes a differential amplifier and a first and a second pull-up transistor for generating a reference voltage. The second pull-up transistor has a gate connected to an output terminal of the differential amplifier. The differential amplifier is such that, when an output voltage thereof previously outputted is at a high level, both the first and second pull-up transistors become conductive so that the reference voltage becomes equilibrium at a high level voltage, and when an output voltage previously outputted is at a low level, the first pull-up transistor becomes conductive and the second pull-up transistor becomes non conductive so that the reference voltage becomes equilibrium at a low level voltage. With this arrangement, a high speed operation of the differential amplifier is realized.

Abstract: Disclosed herein is a semiconductor memory device comprising an N-channel transistor and a P-channel transistor Q33 which are provided in parallel between a sense node and a power supply line, The N-channel transistor has a threshold value of near 0 V and a specified current drive capability. The P-channel transistor Q33 charges the sense node up to the level that is smaller than a power supply voltage by a threshold value thereof and the level at the sense node is then changed by use of the N-channel transistor in accordance with data stored in the memory cell coupled to the sense node.

Abstract: An electrically programmable read only memory device stores data bits each in the form of either high or low threshold level of a memory cell, and an accessed data bit is transferred from a selected memory cell to an output data buffer unit for delivery to a destination, wherein a plurality of output data buffer circuits are provided in the output data buffer unit and are selectively used for the data delivery depending upon current driving capability expected by a customer.

Abstract: An electrically programmable read only memory device stores data bits each in the form of either high or low threshold level of a memory cell, and an accessed data bit is transferred from a selected memory cell to an output data buffer unit for delivery to a destination, wherein a plurality of output data buffer circuits are provided in the output data buffer unit and are selectively used for the data delivery depending upon current driving capability expected by a customer.

Abstract: Electric field stress applied to memory cells is relieved in a semiconductor memory device. For this purpose, an X-decoder circuit applies a low level signal to a selected memory cell in a selected memory cell block of a selected memory cell matrix, and a high level signal to non-selected memory cells in the selected memory cell block, while the X-decoder circuit applies the low level signal to memory cells of non-selected memory cell blocks of the selected memory cell matrix and memory cells of non-selected memory cell matrices.

Abstract: A dynamic random access memory device is equipped with an output data buffer circuit for driving an output data pin, and the output data buffer circuit comprises an output inverter coupled with the data pin, a driving unit responsive to a data bit on a data line pair in the absence of a high-impedance control signal for controlling the output inverter, the driving unit being further operative to cause the output inverter to enter high-impedance state in the presence of the high-impedance control signal, and a switching transistor coupled between the data pin and a constant voltage source and responsive to a preceding signal for coupling the output data pin with the constant voltage source, wherein the high-impedance control signal and the preceding signal are supplied to the output data buffer circuit before reaching the data bit thereto so that power voltage lines are prevented from voltage fluctuation without sacrifice of switching speed.