Patents by Inventor Takaki Kumanomido

Takaki Kumanomido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mark arrangement inspecting method, mask data, and manufacturing method of semiconductor device
    Patent number: 8364437
    Abstract: A method of inspecting a mark arrangement according to an embodiment of the present invention includes: generating mask data in which mark seed data that includes an inspection mark that includes vector information and is not drawn on a mask and mark data is arranged on a scribe line of the mask, calculating coordinates of the inspection mark from a reference position of the mark seed data, detecting an arrangement state of the inspection mark with respect to the reference position by using the coordinates and vector information, and judging whether the mark seed data is correctly arranged by comparing the arrangement state of the inspection mark with an arrangement check rule.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: January 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Morinaga, Kazutaka Ishigo, Takaki Kumanomido
  • MARK ARRANGEMENT INSPECTING METHOD, MASK DATA, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    Publication number: 20100211352
    Abstract: A method of inspecting a mark arrangement according to an embodiment of the present invention includes: generating mask data in which mark seed data that includes an inspection mark that includes vector information and is not drawn on a mask and mark data is arranged on a scribe line of the mask, calculating coordinates of the inspection mark from a reference position of the mark seed data, detecting an arrangement state of the inspection mark with respect to the reference position by using the coordinates and vector information, and judging whether the mark seed data is correctly arranged by comparing the arrangement state of the inspection mark with an arrangement check rule.
    Type: Application
    Filed: December 30, 2009
    Publication date: August 19, 2010
    Inventors: Hiroyuki MORINAGA, Kazutaka Ishigo, Takaki Kumanomido
  • Semiconductor integrated circuits with a protection device
    Patent number: 4881113
    Abstract: The semiconductor integrated circuit comprises a semiconductor substrate having a circuit region, a pad formed at the surface of the semiconductor substrate and forming a PN junction with the semiconductor substrate, and first and second electrodes. Each electrode contacts the semiconductor region such that the contacting regions of the electrodes face each other with a ring shaped region between.
    Type: Grant
    Filed: October 29, 1986
    Date of Patent: November 14, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Momodomi, Mitsugi Ogura, Takaki Kumanomido