Abstract: Disclosed is a solid-state imaging device including a pixel array, two vertical scanning circuits, and a control part. The pixel array has a plurality of pixels arranged in a two-dimensional matrix form. The two vertical scanning circuits are configured to sequentially select and scan each of the pixels in a vertical direction per row. The control part is configured to generate, based on a mode signal corresponding to an imaging mode, a driving switch signal to stop driving of one of the two vertical scanning circuits.

Abstract: Disclosed is a solid-state imaging device including a pixel array, two vertical scanning circuits, and a control part. The pixel array has a plurality of pixels arranged in a two-dimensional matrix form. The two vertical scanning circuits are configured to sequentially select and scan each of the pixels in a vertical direction per row. The control part is configured to generate, based on a mode signal corresponding to an imaging mode, a driving switch signal to stop driving of one of the two vertical scanning circuits.

Abstract: Disclosed is a solid-state imaging device including a pixel array, two vertical scanning circuits, and a control part. The pixel array has a plurality of pixels arranged in a two-dimensional matrix form. The two vertical scanning circuits are configured to sequentially select and scan each of the pixels in a vertical direction per row. The control part is configured to generate, based on a mode signal corresponding to an imaging mode, a driving switch signal to stop driving of one of the two vertical scanning circuits.

Abstract: Disclosed is a solid-state imaging device including a pixel array, two vertical scanning circuits, and a control part. The pixel array has a plurality of pixels arranged in a two-dimensional matrix form. The two vertical scanning circuits are configured to sequentially select and scan each of the pixels in a vertical direction per row. The control part is configured to generate, based on a mode signal corresponding to an imaging mode, a driving switch signal to stop driving of one of the two vertical scanning circuits.

Abstract: Disclosed is a solid-state imaging device including a pixel array, a pixel signal generation part, and a control part. The pixel signal generation part includes a comparator and a counter. In a case where an enable signal is supplied from the control part, a count value of the counter in a D-phase period where a signal level is detected is set as a limit value regardless of an output of the comparator when a count value of the counter in a P-phase period where a reset level is detected is a limit value.

Abstract: Disclosed is a solid-state imaging device including a pixel array, two vertical scanning circuits, and a control part. The pixel array has a plurality of pixels arranged in a two-dimensional matrix form. The two vertical scanning circuits are configured to sequentially select and scan each of the pixels in a vertical direction per row. The control part is configured to generate, based on a mode signal corresponding to an imaging mode, a driving switch signal to stop driving of one of the two vertical scanning circuits.

Abstract: Disclosed is a solid-state imaging device including a pixel array, a pixel signal generation part, and a control part. The pixel signal generation part includes a comparator and a counter. In a case where an enable signal is supplied from the control part, a count value of the counter in a D-phase period where a signal level is detected is set as a limit value regardless of an output of the comparator when a count value of the counter in a P-phase period where a reset level is detected is a limit value.

Abstract: Disclosed is a solid-state imaging device including a pixel array, two vertical scanning circuits, and a control part. The pixel array has a plurality of pixels arranged in a two-dimensional matrix form. The two vertical scanning circuits are configured to sequentially select and scan each of the pixels in a vertical direction per row. The control part is configured to generate, based on a mode signal corresponding to an imaging mode, a driving switch signal to stop driving of one of the two vertical scanning circuits.

Abstract: According to a signal generating circuit including a delay-locked loop, a driving device including the signal generating circuit, and an image capturing apparatus including the signal generating circuit, when a rising edge designation signal for designating a predetermined rise time and a falling edge designation signal for designating a predetermined fall time are input, the signal generating circuit selects, from among a plurality of delay signals, a first delay signal rising at the time designated by the rising edge designation signal and a second delay signal rising at the time designated by the falling edge designation signal and outputs an output signal rising at the predetermined rise time and falling at the predetermined fall time by performing arithmetic processing on the first delay signal and the second delay signal.

Abstract: A data processing device includes a comparing unit that compares a reference signal and respective processing object signals, a count-period control unit that determines a count period to perform count processing, a count unit that performs the count processing in the count period designated by the count-period control unit, stores a count value, applies the count processing to both a subtraction element and an addition element in an identical mode of any one of an up-count mode and a down-count mode, and starts the count processing for a following processing object signal using a count value for a preceding processing object signal as an initial value, and a correcting unit that corrects digital data of a multiply-accumulate result of the plural processing object signals to digital data in which a count value is corrected.

Abstract: According to a signal generating circuit including a delay-locked loop, a driving device including the signal generating circuit, and an image capturing apparatus including the signal generating circuit, when a rising edge designation signal for designating a predetermined rise time and a falling edge designation signal for designating a predetermined fall time are input, the signal generating circuit selects, from among a plurality of delay signals, a first delay signal rising at the time designated by the rising edge designation signal and a second delay signal rising at the time designated by the falling edge designation signal and outputs an output signal rising at the predetermined rise time and falling at the predetermined fall time by performing arithmetic processing on the first delay signal and the second delay signal.

Abstract: A plurality of light emitting diode pellets arranged on a base are surrounded by a partition member and an outer frame member fixed on the base to mount an elongated lens on the opening portion thereof. A certain number of partition members are arranged between the base and the lens having recessed portions so as to partition each pellet or groups of several pellets. The upper ends of the partition members are inserted into recessed portions of the lens. Thus, when an arbitrary light emitting diode pellet is energized, light from the energized pellet does not spread to the non-light emitting pellet portions, thus clearly discriminating between the light emitting portions and non-light emitting portions.