Abstract: Disclosed is a reagent for activated partial thromboplastin time measurement including an ellagic acid compound, a phospholipid, and a polyvinyl alcohol compound.

Abstract: An arithmetic device calculates the surface potential of a silicon layer by performing computation based on a mathematical expression and device parameters stored in a storage device. Likewise, the arithmetic device calculates the surface potential of a bulk layer under a buried oxide film when the silicon layer is in a partially depleted state and when the silicon is in a fully depleted state. The arithmetic device then performs computation based on the calculated surface potential of the silicon layer, the calculated surface potential of the bulk layer, and mathematical expressions stored in the storage device, and obtains the surface potential of the bulk layer by iterative calculation. The arithmetic device performs computation based on the surface potential of the bulk layer obtained by iterative calculation and mathematical expressions stored in the storage device, and calculates the lower surface potential of the silicon layer.

Abstract: An arithmetic device calculates the surface potential of a silicon layer by performing computation based on a mathematical expression and device parameters stored in a storage device. Likewise, the arithmetic device calculates the surface potential of a bulk layer under a buried oxide film when the silicon layer is in a partially depleted state and when the silicon is in a fully depleted state. The arithmetic device then performs computation based on the calculated surface potential of the silicon layer, the calculated surface potential of the bulk layer, and mathematical expressions stored in the storage device, and obtains the surface potential of the bulk layer by, iterative calculation. The arithmetic device performs computation based on the surface potential of the bulk layer obtained by iterative calculation and mathematical expressions stored in the storage device, and calculates the lower surface potential of the silicon layer.

Abstract: An indication instrument with improved illumination efficiency. The indication instrument has an indication panel (100), an indication plate (200) on which index parts (201) are disposed along the outer periphery of the indication panel (100), a pointer (11) for indicating the index parts (201), a drive source (7) for driving the pointer (11), and an indication plate light source (light source) (700) for illuminating the indication plate (200). The pointer (11) is routed around the rear of the indication panel (100) to reach the front of the indication plate (200). The indication instrument further comprises a frame (300) for joining to each other the indication panel (100), the indication plate (200), and the light source (700). An illumination chamber (R1) for guiding the light of the light source (700) to the indication plate (200) is formed in the frame (300).

Abstract: The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on sites in the semiconductor integrated circuit where a fault is likely to occur or information required to reduce such faults. In addition, the fault detecting method and the layout method perform ordering of faults with their likelihood and weighting of the faults, taking into consideration physical information on a mask pattern within a chip or records of actual use of cells or functional blocks.

Abstract: An indication instrument with improved illumination efficiency. The indication instrument has an indication panel (100), an indication plate (200) on which index parts (201) are disposed along the outer periphery of the indication panel (100), a pointer (11) for indicating the index parts (201), a drive source (7) for driving the pointer (11), and an indication plate light source (light source) (700) for illuminating the indication plate (200). The pointer (11) is routed around the rear of the indication panel (100) to reach the front of the indication plate (200). The indication instrument further comprises a frame (300) for joining to each other the indication panel (100), the indication plate (200), and the light source (700). An illumination chamber (R1) for guiding the light of the light source (700) to the indication plate (200) is formed in the frame (300).

Abstract: In the inventive semiconductor integrated circuit verification method, based upon expected values of a signal from an integrated circuit, which are obtained by RTL verification or the like, and upon signal delay information obtained by static timing analysis (STA), expected value comparison times (strobe times) of a test pattern are extracted, or expected value verification as to whether values of an actually produced signal match the expected values is performed. In this manner, the inventive method allows the test pattern to be prepared with consideration given to variation in the LSI process, temperature, voltage and the like and to constraints of the test apparatus.

Abstract: The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on sites in the semiconductor integrated circuit where a fault is likely to occur or information required to reduce such faults. In addition, the fault detecting method and the layout method perform ordering of faults with their likelihood and weighting of the faults, taking into consideration physical information on a mask pattern within a chip or records of actual use of cells or functional blocks.

Abstract: For the purpose of readily specifying a portion of the circuit which has a high possibility of error occurring due to a variation in the supply voltage so that the specified vulnerable portion is countermeasured in a mask layout process, a simulation section simulates the operation of a semiconductor integrated circuit to obtain a transition timing of an input signal that is input to each circuit element. A simultaneous-operation circuit element number detecting section detects, based on a result of the simulation, the number of circuit elements which are supplied with the supply voltage through a common power supply line and in which transition timings of input signals occur within a predetermined time interval (e.g., 0.3 ns or shorter). A supply voltage variation level estimating section estimates the variation level of the supply voltage according to the number of circuit elements which is detected by the simultaneous-operation circuit element number detecting section.

Abstract: A method is provided for designing a semiconductor integrated circuit including a plurality of clock groups which are designed to be supplied with their respective clock signals. The method is improved by supplying plural kinds of clock signals for performing a scan testing respectively to the clock groups, the respective clock signals having different duty factors in at least a part of the clock groups. This prevents circuits on the plurality of scan lines from operating simultaneously, thus suppressing power consumption during a clock operation, allowing highly accurate testing.

Abstract: A method of verifying a semiconductor integrated circuit according to the invention does not compare expected values based on a strobe every cycle but executes a verification on the basis of a signal transition (change) point. At the same time, the verifying method is intended for verifying a path in a circuit through which a signal transition (change) in a result to be output is sent, and can find the drawbacks of a circuit and a pattern in a more upstream process for a design with higher precision as compared with the conventional art so that quality of a design can be enhanced. By using information about the path through which the signal transition is output to carry out an inspection, moreover, it is possible to finally inspect (test) an LSI with high precision and quality.

Abstract: The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on sites in the semiconductor integrated circuit where a fault is likely to occur or information required to reduce such faults. In addition, the fault detecting method and the layout method perform ordering of faults with their likelihood and weighting of the faults, taking into consideration physical information on a mask pattern within a chip or records of actual use of cells or functional blocks.

Abstract: The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on sites in the semiconductor integrated circuit where a fault is likely to occur or information required to reduce such faults. In addition, the fault detecting method and the layout method perform ordering of faults with their likelihood and weighting of the faults, taking into consideration physical information on a mask pattern within a chip or records of actual use of cells or functional blocks.

Abstract: The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on sites in the semiconductor integrated circuit where a fault is likely to occur or information required to reduce such faults. In addition, the fault detecting method and the layout method perform ordering of faults with their likelihood and weighting of the faults, taking into consideration physical information on a mask pattern within a chip or records of actual use of cells or functional blocks.

Abstract: In the inventive semiconductor integrated circuit verification method, based upon expected values of a signal from an integrated circuit, which are obtained by RTL verification or the like, and upon signal delay information obtained by static timing analysis (STA), expected value comparison times (strobe times) of a test pattern are extracted, or expected value verification as to whether values of an actually produced signal match the expected values is performed. In this manner, the inventive method allows the test pattern to be prepared with consideration given to variation in the LSI process, temperature, voltage and the like and to constraints of the test apparatus.

Abstract: For the purpose of readily specifying a portion of the circuit which has a high possibility of error occurring due to a variation in the supply voltage so that the specified vulnerable portion is countermeasured in a mask layout process, a simulation section simulates the operation of a semiconductor integrated circuit to obtain a transition timing of an input signal that is input to each circuit element. A simultaneous-operation circuit element number detecting section detects, based on a result of the simulation, the number of circuit elements which are supplied with the supply voltage through a common power supply line and in which transition timings of input signals occur within a predetermined time interval (e.g., 0.3 ns or shorter). A supply voltage variation level estimating section estimates the variation level of the supply voltage according to the number of circuit elements which is detected by the simultaneous-operation circuit element number detecting section.

Abstract: A method is provided for designing a semiconductor integrated circuit including a plurality of clock groups which are designed to be supplied with their respective clock signals. The method is improved by supplying plural kinds of clock signals for performing a scan testing respectively to the clock groups, the respective clock signals having different duty factors in at least a part of the clock groups. This prevents circuits on the plurality of scan lines from operating simultaneously, thus suppressing power consumption during a clock operation, allowing highly accurate testing.