Patents by Inventor Takako Chinone

Takako Chinone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9070836
    Abstract: A semiconductor light-emitting device includes a lamination of semiconductor layers including a first layer of a first conductivity type, an active layer, and a second layer of a second conductivity type; a transparent conductive film formed on a principal surface of the lamination and having an opening; a pad electrode formed on part the opening; and a wiring electrode connected with the pad electrode, formed on another part of the opening while partially overlapping the transparent conductive film; wherein contact resistance between the transparent conductive film and the lamination is larger than contact resistance between the wiring electrode and the lamination. Field concentration at the wiring electrode upon application of high voltage is mitigated by the overlapping transparent conductive film.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: June 30, 2015
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Noriko Nihei, Takako Chinone
  • Patent number: 9048090
    Abstract: A method of manufacturing a semiconductor element includes forming a first bonding layer containing a metal, which forms a eutectic crystal with Au, on a first substrate to provide a first laminated body. The method also includes forming an element structure layer having a semiconductor layer on a second substrate. The method also includes forming a second bonding layer on the element structure layer to provide a second laminated body. The second bonding layer has a metal underlayer containing a metal, which forms a eutectic crystal with Au. The second bonding layer also has a surface layer that contains Au. The method also includes performing heating pressure-bonding on the first and second laminated bodies with the first and second bonding layers facing each other. The heating temperature of the second substrate in the heating pressure-bonding is higher than the heating temperature of the first substrate.
    Type: Grant
    Filed: March 17, 2013
    Date of Patent: June 2, 2015
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Takako Chinone, Mamoru Miyachi, Tatsuma Saito, Takanobu Akagi
  • Patent number: 9035332
    Abstract: A semiconductor light emitting element array contains: a support substrate; a plurality of semiconductor light emitting elements disposed on said support substrate, a pair of adjacent semiconductor light emitting elements being separated by street, each of the semiconductor light emitting elements including; a first electrode formed on the support substrate, a semiconductor lamination formed on the first electrode and including a stack of a first semiconductor layer having a first conductivity type, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer, and having a second conductivity type different from the first conductivity type, and a second electrode selectively formed on the second semiconductor layer of the semiconductor lamination; and connection member having electrical insulating property and optically propagating property, disposed to cover at least part of the street between a pair of adjacent semiconductor laminations.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 19, 2015
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Tatsuma Saito, Mamoru Miyachi, Takako Chinone, Noriko Nihei, Takanobu Akagi
  • Patent number: 9024332
    Abstract: A semiconductor light emitting element has a cross-sectional structure comprising a support substrate, a semiconductor lamination located over the support substrate, and a joint layer located between the semiconductor lamination and the support substrate, containing a first jointing layer located on the semiconductor lamination side and a second jointing layer located on the support substrate side. In the plan view, the semiconductor lamination has corner portions and side portions along the periphery, the first jointing layer is encompassed by the second jointing layer, the second jointing layer is encompassed by the semiconductor lamination, and an annular region defined between outlines of the semiconductor lamination and of the first jointing layer has first portions corresponding to the corner portions of the semiconductor lamination and second portions corresponding to the side portions of the semiconductor lamination, widths of the first portions being narrower than widths of the second portions.
    Type: Grant
    Filed: March 17, 2013
    Date of Patent: May 5, 2015
    Assignee: Stanley Electronic Co., Ltd.
    Inventors: Mamoru Miyachi, Tatsuma Saito, Takako Chinone, Takanobu Akagi
  • Patent number: 8916396
    Abstract: A method of manufacturing a semiconductor element includes forming an element structure layer having a semiconductor layer, on a first substrate. The method also includes forming a first bonding layer on the element structure layer. The method also includes forming a second bonding layer on a second substrate. The method also includes performing heating pressure-bonding on the first and second bonding layers, with the first and second bonding layers facing each other. One of the first bonding layer and the second bonding layer is an AU layer, and the other is an AuSn layer. The AuSn layer has a surface layer having an Sn content of between 85 wt % (inclusive) and 95 wt % (inclusive).
    Type: Grant
    Filed: March 17, 2013
    Date of Patent: December 23, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Takako Chinone, Mamoru Miyachi, Tatsuma Saito, Takanobu Akagi
  • Patent number: 8658440
    Abstract: A nitride semiconductor light emitting device is formed by: forming a resist pattern on a first nitride semiconductor layer formed on a substrate, the resist pattern having a region whose inclination angle relative to a substrate surface changes smoothly as viewed in a cross section perpendicular to the substrate surface; etching the substrate by using the resist pattern as a mask to transfer the resist pattern to the first nitride semiconductor layer; and forming an light emitting layer on the patterned first nitride semiconductor layer. The nitride semiconductor light emitting device can emit near-white light or have a wavelength range generally equivalent to or near visible light range.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 25, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Ji-Hao Liang, Masahiko Tsuchiya, Takako Chinone, Masataka Kajikawa
  • Patent number: 8637889
    Abstract: A semiconductor light emitting device includes: a semiconductor lamination including a first semiconductor layer of a first conductivity type, an active layer formed on the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed on the active layer; a rhodium (Rh) layer formed on one surface of the semiconductor lamination; a light reflecting layer containing Ag, formed on the Rh layer and having an area smaller than the Rh layer; and a cap layer covering the light reflecting layer. Migration of Ag is suppressed.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: January 28, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Takako Chinone
  • Publication number: 20130248918
    Abstract: A semiconductor light emitting element has a cross-sectional structure comprising a support substrate, a semiconductor lamination located over the support substrate, and a joint layer located between the semiconductor lamination and the support substrate, containing a first jointing layer located on the semiconductor lamination side and a second jointing layer located on the support substrate side. In the plan view, the semiconductor lamination has corner portions and side portions along the periphery, the first jointing layer is encompassed by the second jointing layer, the second jointing layer is encompassed by the semiconductor lamination, and an annular region defined between outlines of the semiconductor lamination and of the first jointing layer has first portions corresponding to the corner portions of the semiconductor lamination and second portions corresponding to the side portions of the semiconductor lamination, widths of the first portions being narrower than widths of the second portions.
    Type: Application
    Filed: March 17, 2013
    Publication date: September 26, 2013
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventors: Mamoru MIYACHI, Tatsuma SAITO, Takako CHINONE, Takanobu AKAGI
  • Publication number: 20130241061
    Abstract: A method of manufacturing a semiconductor element includes forming a first bonding layer containing a metal, which forms a eutectic crystal with Au, on a first substrate to provide a first laminated body. The method also includes forming an element structure layer having a semiconductor layer on a second substrate. The method also includes forming a second bonding layer on the element structure layer to provide a second laminated body. The second bonding layer has a metal underlayer containing a metal, which forms a eutectic crystal with Au. The second bonding layer also has a surface layer that contains Au. The method also includes performing heating pressure-bonding on the first and second laminated bodies with the first and second bonding layers facing each other. The heating temperature of the second substrate in the heating pressure-bonding is higher than the heating temperature of the first substrate.
    Type: Application
    Filed: March 17, 2013
    Publication date: September 19, 2013
    Inventors: Takako Chinone, Mamoru Miyachi, Tatsuma Saito, Takanobu Akagi
  • Publication number: 20130244361
    Abstract: A method of manufacturing a semiconductor element includes forming an element structure layer having a semiconductor layer, on a first substrate. The method also includes forming a first bonding layer on the element structure layer. The method also includes forming a second bonding layer on a second substrate. The method also includes performing heating pressure-bonding on the first and second bonding layers, with the first and second bonding layers facing each other. One of the first bonding layer and the second bonding layer is an AU layer, and the other is an AuSn layer. The AuSn layer has a surface layer having an Sn content of between 85 wt % (inclusive) and 95 wt % (inclusive).
    Type: Application
    Filed: March 17, 2013
    Publication date: September 19, 2013
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventors: Takako Chinone, Mamoru Miyachi, Tatsuma Saito, Takanobu Akagi
  • Patent number: 8530256
    Abstract: (a) Forming on a growth substrate a void-containing layer that is made of a group III nitride compound semiconductor and contains voids. (b) Forming on the void-containing layer an n-type layer that is made of an n-type group III nitride compound semiconductor and serves to close the voids. (c) Forming on the n-type layer an active layer made of a group III nitride compound semiconductor. (d) Forming on the active layer a p-type layer made of a p-type group III nitride compound semiconductor. (e) Bonding a support substrate above the p-type layer. (f) Peeling off the growth substrate at the boundary where the void are produced. (g) Planarizing the n-type layer. Step (b) comprises (b1) forming part of the n-type layer under conditions where horizontal growth is relatively weak and (b2) forming the remaining part of the n-type layer under conditions where horizontal growth is relatively strong.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 10, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Yasuyuki Shibata, Ji-Hao Liang, Takako Chinone
  • Patent number: 8338202
    Abstract: In a method for manufacturing a semiconductor device, a first conductivity type semiconductor layer and a second conductivity type semiconductor layer are sequentially grown on a growth substrate. Then, an electrode layer is formed on the second conductivity type semiconductor layer. Then, a support body is adhered to the electrode layer by providing at least one adhesive layer therebetween. Finally, at least a part of the growth substrate is removed. In this case, the adhesive layer is removable from the electrode layer.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: December 25, 2012
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Takako Chinone, Shinichi Tanaka, Sho Iwayama, Yusuke Yokobayashi, Satoshi Tanaka
  • Publication number: 20120231608
    Abstract: (a) Forming on a growth substrate a void-containing layer that is made of a group III nitride compound semiconductor and contains voids. (b) Forming on the void-containing layer an n-type layer that is made of an n-type group III nitride compound semiconductor and serves to close the voids. (c) Forming on the n-type layer an active layer made of a group III nitride compound semiconductor. (d) Forming on the active layer a p-type layer made of a p-type group III nitride compound semiconductor. (e) Bonding a support substrate above the p-type layer. (f) Peeling off the growth substrate at the boundary where the void are produced. (g) Planarizing the n-type layer. Step (b) comprises (b1) forming part of the n-type layer under conditions where horizontal growth is relatively weak and (b2) forming the remaining part of the n-type layer under conditions where horizontal growth is relatively strong.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 13, 2012
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventors: Yasuyuki SHIBATA, Ji-Hao Liang, Takako Chinone
  • Patent number: 8236672
    Abstract: A cavity-containing layer having a plurality of cavities is formed on a growth substrate by carrying out in alternating fashion a plurality of cycles of a first and second growth steps of growing a group III nitride at growth rates different from each other. The semiconductor epitaxial layer is subsequently formed on the cavity-containing layer, after which a support substrate is bonded to the semiconductor epitaxial layer. The growth substrate is separated from the cavity-containing layer.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: August 7, 2012
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Takako Chinone, Ji-Hao Liang, Yasuyuki Shibata, Jiro Higashino
  • Patent number: 8158993
    Abstract: A nitride semiconductor light emitting device is formed by: forming a resist pattern on a first nitride semiconductor layer formed on a substrate, the resist pattern having a region whose inclination angle relative to a substrate surface changes smoothly as viewed in a cross section perpendicular to the substrate surface; etching the substrate by using the resist pattern as a mask to transfer the resist pattern to the first nitride semiconductor layer; and forming an light emitting layer on the patterned first nitride semiconductor layer. The nitride semiconductor light emitting device can emit near-white light or have a wavelength range generally equivalent to or near visible light range.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: April 17, 2012
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Ji-Hao Liang, Masahiko Tsuchiya, Takako Chinone, Masataka Kajikawa
  • Publication number: 20120077298
    Abstract: A nitride semiconductor light emitting device is formed by: forming a resist pattern on a first nitride semiconductor layer formed on a substrate, the resist pattern having a region whose inclination angle relative to a substrate surface changes smoothly as viewed in a cross section perpendicular to the substrate surface; etching the substrate by using the resist pattern as a mask to transfer the resist pattern to the first nitride semiconductor layer; and forming an light emitting layer on the patterned first nitride semiconductor layer. The nitride semiconductor light emitting device can emit near-white light or have a wavelength range generally equivalent to or near visible light range.
    Type: Application
    Filed: December 6, 2011
    Publication date: March 29, 2012
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventors: Ji-Hao LIANG, Masahiko Tsuchiya, Takako Chinone, Masataka Kajikawa
  • Patent number: 8111350
    Abstract: A plurality of protrusions is formed on the C-plane substrate with a corundum structure. A base film made of a III-V compound semiconductor including Ga and N is formed on the surface of the substrate. The surface of the base film is flatter than the surface of the substrate. A light emitting structure including Ga and N is disposed on the base film. The protrusions are regularly arranged in a first direction that is tilted by less than 15 degrees with respect to the a-axis of the base film and in a second direction that is orthogonal to the first direction. Each protrusion has two first parallel sides tilted by less than 15 degrees relative to an m-axis and two second parallel sides tilted by less than 15 degrees relative to the a-axis. An interval between the two second sides is wider than an interval between the two first sides.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: February 7, 2012
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Jiro Higashino, Ji-Hao Liang, Takako Chinone, Yasuyuki Shibata
  • Patent number: 8008170
    Abstract: There is provided a method for manufacturing a semiconductor device in which a selective growth mask for partially covering a growth substrate is formed on a growth substrate; a buffer layer that is thicker than the mask is formed on a non-mask part not covered by the mask on the growth substrate, and a predetermined facet is exposed on the surface of the buffer layer; a semiconductor film is laterally grown using the buffer layer as a starting point, and a lateral growth layer for covering the mask is formed while cavities are formed on the upper part of the mask; and a device function layer is epitaxially grown on the lateral growth layer. The cavity formation step includes a first step for growing a semiconductor film at a growth rate and a second step for growing another semiconductor film at another growth rate mutually different from the first growth rate, wherein the first and second steps are carried out a plurality of times in alternating fashion.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: August 30, 2011
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Ji-Hao Liang, Takako Chinone, Yasuyuki Shibata, Jiro Higashino
  • Publication number: 20110175105
    Abstract: A plurality of protrusions is formed on the C-plane substrate with a corundum structure. A base film made of a III-V compound semiconductor including Ga and N is formed on the surface of the substrate. The surface of the base film is flatter than the surface of the substrate. A light emitting structure including Ga and N is disposed on the base film. The protrusions are regularly arranged in a first direction that is tilted by less than 15 degrees with respect to the a-axis of the base film and in a second direction that is orthogonal to the first direction. Each protrusion has two first parallel sides tilted by less than 15 degrees relative to an m-axis and two second parallel sides tilted by less than 15 degrees relative to the a-axis. An interval between the two second sides is wider than an interval between the two first sides.
    Type: Application
    Filed: January 13, 2011
    Publication date: July 21, 2011
    Applicant: STANLEY ELECTRIC CO., LTD.
    Inventors: Jiro HIGASHINO, Ji-Hao LIANG, Takako CHINONE, Yasuyuki SHIBATA
  • Publication number: 20100155740
    Abstract: A cavity-containing layer having a plurality of cavities is formed on a growth substrate by carrying out in alternating fashion a plurality of cycles of a first and second growth steps of growing a group III nitride at growth rates different from each other. The semiconductor epitaxial layer is subsequently formed on the cavity-containing layer, after which a support substrate is bonded to the semiconductor epitaxial layer. The growth substrate is separated from the cavity-containing layer.
    Type: Application
    Filed: December 14, 2009
    Publication date: June 24, 2010
    Applicant: Stanley Electric Co., Ltd.
    Inventors: Takako CHINONE, Ji-Hao Liang, Yasuyuki Shibata, Jiro Higashino