Patents by Inventor Takako Fujisawa

Takako Fujisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8036447
    Abstract: A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: October 11, 2011
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Koichi Hayakawa, Hiroshi Miyai, Masaaki Nojiri, Michio Nakano, Takako Fujisawa, Dai Fujii
  • Patent number: 7889911
    Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: February 15, 2011
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Michio Nakano, Shigeya Tanaka, Yoshiyuki Momiyama, Takashi Hiroi, Kazuya Hayashi, Dai Fujii, Takako Fujisawa, Atsushi Ichige, Ichiro Kawashima
  • Publication number: 20100008564
    Abstract: A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.
    Type: Application
    Filed: September 22, 2009
    Publication date: January 14, 2010
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Koichi HAYAKAWA, Hiroshi Miyai, Masaaki Nojiri, Michio Nakano, Takako Fujisawa, Dai Fujii
  • Publication number: 20080285841
    Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.
    Type: Application
    Filed: July 10, 2008
    Publication date: November 20, 2008
    Inventors: Michio NAKANO, Shigeya Tanaka, Yoshiyuki Momiyama, Takashi Hiroi, Kazuya Hayashi, Dai Fujii, Takako Fujisawa, Atsushi Ichige, Ichiro Kawashima
  • Patent number: 7421110
    Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: September 2, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Michio Nakano, Shigeya Tanaka, Yoshiyuki Momiyama, Takashi Hiroi, Kazuya Hayashi, Dai Fujii, Takako Fujisawa, Atsushi Ichige, Ichiro Kawashima
  • Publication number: 20060171593
    Abstract: A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.
    Type: Application
    Filed: February 1, 2006
    Publication date: August 3, 2006
    Inventors: Koichi Hayakawa, Hiroshi Miyai, Masaaki Nojiri, Michio Nakano, Takako Fujisawa, Dai Fujii
  • Publication number: 20040170313
    Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.
    Type: Application
    Filed: February 19, 2004
    Publication date: September 2, 2004
    Inventors: Michio Nakano, Shigeya Tanaka, Yoshiyuki Momiyama, Takashi Hiroi, Kazuya Hayashi, Dai Fujii, Takako Fujisawa, Atsushi Ichige, Ichiro Kawashima