Patents by Inventor Takako Funakoshi

Takako Funakoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8093723
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: January 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni, Kousuke Okuyama
  • Publication number: 20110204486
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 25, 2011
    Inventors: Takako FUNAKOSHI, Eiichi MURAKAMI, Kazumasa YANAGISAWA, Kan TAKEUCHI, Hideo AOKI, Hizuru YAMAGUCHI, Takayuki OSHIMA, Kazuyuki TSUNOKUNI, Kousuke OKUYAMA
  • Patent number: 7977238
    Abstract: A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: July 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni, Kousuke Okuyama
  • Patent number: 7786585
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: August 31, 2010
    Assignee: Renesas Electronics Corp.
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni, Kousuke Okuyama
  • Publication number: 20100203724
    Abstract: A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
    Type: Application
    Filed: April 21, 2010
    Publication date: August 12, 2010
    Inventors: Takako FUNAKOSHI, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni, Kousuke Okuyama
  • Publication number: 20080303158
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
    Type: Application
    Filed: August 8, 2008
    Publication date: December 11, 2008
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni, Kousuke Okuyama
  • Patent number: 7411301
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: August 12, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni, Kousuke Okuyama
  • Patent number: 7023091
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: April 4, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni
  • Publication number: 20060027928
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
    Type: Application
    Filed: September 30, 2005
    Publication date: February 9, 2006
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni
  • Publication number: 20040065961
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a Cu wiring is not smaller than about 0.9 &mgr;m and smaller than about 1.44 &mgr;m and the width of another Cu wiring and the diameter of a plug are about 0.18 &mgr;m, there are arranged two or more plugs which connect the Cu wirings and another Cu wirings electrically with each other on the Cu wiring.
    Type: Application
    Filed: June 20, 2003
    Publication date: April 8, 2004
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni