Patents by Inventor Takako Kondo

Takako Kondo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6417706
    Abstract: An internal clock generation circuit according to the present invention comprises a phase comparator, a shift register, a filter, a monitor circuit, and a plurality of delay lines such as first and second delay lines. The first delay line has delay steps each larger than that of the second delay line. The first delay line is first used to generate a clock minimized in phase difference with respect to an external clock. The clock signal is inputted to the second delay line to perform fine adjustment to the phase difference.
    Type: Grant
    Filed: September 13, 2001
    Date of Patent: July 9, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takako Kondo
  • Publication number: 20020005746
    Abstract: An internal clock generation circuit according to the present invention comprises a phase comparator, a shift register, a filter, a monitor circuit, and a plurality of delay lines such as first and second delay lines. The first delay line has delay steps each larger than that of the second delay line. The first delay line is first used to generate a clock minimized in phase difference with respect to an external clock. The clock signal is inputted to the second delay line to perform fine adjustment to the phase difference.
    Type: Application
    Filed: September 13, 2001
    Publication date: January 17, 2002
    Inventor: Takako Kondo
  • Patent number: 6297680
    Abstract: An internal clock generation circuit according to the present invention includes a phase comparator, a shift register, a filter, a monitor circuit, and a plurality of delay lines such as first and second delay lines. The first delay line has delay steps each larger than that of the second delay line. The first delay line is first used to generate a clock minimized in phase difference with respect to an external clock. The clock signal is inputted to the second delay line to perform fine adjustment to the phase difference.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: October 2, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takako Kondo