Abstract: In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.

Abstract: In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.

Abstract: A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.

Abstract: As a method for considering the adverse influence of the stresses caused form the pad, two sorts of methods are provided. As one method, while delay variation values of cells caused by an adverse influence of stresses are calculated, the calculated delay variation values are applied to the cells so as to perform a timing analysis, and the like by considering the adverse influence of the stresses. Then, in order that a flip chip type LSI is designed by employing a result of the above-described analysis in such a manner that the adverse influence of the stresses applied from the pad is not given to vias, wiring lines, and cells located under the pad, such a physical structure that no via is arranged under the pad is employed.

Abstract: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

Abstract: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

Abstract: In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.

Abstract: The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.

Abstract: The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.

Abstract: The semiconductor integrated circuit of the present invention comprises a clock circuit for generating a clock signal. The clock circuit comprises a clock control circuit for controlling propagation of the clock signal. The clock control circuit comprises a burn-in control signal input terminal for inputting a burn-in control signal that controls operation state of the clock circuit when performing burn-in processing, and a clock control signal output terminal for outputting the clock signal. The clock control circuit controls propagation of the clock signal outputted from the clock control signal output terminal based on the burn-in control signal inputted to the burn-in control signal input terminal.

Abstract: In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

Abstract: A circuit from which a buffer and an inverter are removed without changing logic is displayed. Such a circuit is obtained by a first or a second method. With the first method, all buffers which do not change logic and, when a clock path is divided at a branch point of wiring, all pairs of inverters located on each divided clock path are removed from the clock circuit. With the second method, a logic element located on a plurality of clock paths is copied and added to the clock circuit, all buffers which do not change logic and all pairs of inverters located between logic elements other than the above buffers are removed, and redundant partial circuits, if any, realizing the same logic and being located on a plurality of clock paths are removed. Thus, the clock circuit can be displayed so as to facilitate a designer's understanding of logic.

Abstract: The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.