Patents by Inventor Takako Okada

Takako Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6826517
    Abstract: An electronic device simulator includes a three-dimensional lumped device model, a three-dimensional visco-elastic process simulation model and a material design model that are interlinked with each other. The three-dimensional lumped device element model comprises a Poisson's equation model, an electron continuity equation model, a hole continuity equation model, a Maxwell's equations model, an eddy current equation model, and an Ohm's law equation model. The simulator accounts for the three dimensional characteristics of the circuit to determine circuit performance.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: November 30, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takako Okada
  • Publication number: 20020123872
    Abstract: An electronic device simulator includes a three-dimensional lumped device model, a three-dimensional visco-elastic process simulation model and a material design model that are interlinked with each other. The three-dimensional lumped device element model comprises a Poisson's equation model, an electron continuity equation model, a hole continuity equation model, a Maxwell's equations model, an eddy current equation model, and an Ohm's law equation model. The simulator accounts for the three dimensional characteristics of the circuit to determine circuit performance.
    Type: Application
    Filed: December 21, 2000
    Publication date: September 5, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Takako Okada
  • Patent number: 6185472
    Abstract: A semiconductor device manufacturing method capable of proceeding semiconductor device manufacturing processes according to predetermined schedules or while correcting them without testpieces is provided. The method includes the steps of collecting actually observed data during at least one of plural steps, obtaining prediction data in at least one of plural steps by using an ab initio molecular dynamics process simulator or a molecular dynamics simulator, comparing and verifying the prediction data and the actually observed data sequentially at real time, and correcting and processing the plural manufacturing process factors sequentially at real time if a difference in significance is recognized between set values for the plural manufacturing process factors and the plural manufacturing process factors estimated from the actually observed data according to comparison and verification.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: February 6, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Onga, Takako Okada, Hiroshi Tomita, Kikuo Yamabe, Haruo Okano
  • Patent number: 6093243
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: July 25, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 6066872
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: May 23, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5879447
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5582640
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: December 10, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5514904
    Abstract: A semiconductor device includes a monocrystalline silicon substrate, an insulating film consisting of a monocrystalline silicon oxide formed on the surface of the monocrystalline silicon substrate, and a conductive film formed on the insulating film. The monocrystalline silicon substrate has a (100) plane orientation, the insulating film essentially consists of .beta.-cristobalite having a unit structure in a P4.sub.1 2.sub.1 2 structural expression in such a manner that every other silicon atoms of four silicon atoms aligned about a C-axis are arranged on two adjacent silicon atoms aligned in a 110! direction on an Si (100) plane, and that a plane including the C-axis of the .beta.-cristobalite and the 110! direction is set perpendicular to the (100) plane.
    Type: Grant
    Filed: August 26, 1994
    Date of Patent: May 7, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Onga, Takako Okada, Kouichirou Inoue, Yoshiaki Matsushita, Kikuo Yamabe, Hiroaki Hazama, Haruo Okano