Abstract: A semiconductor circuit device which has a first stage logic circuit for receiving an external input signal and a plurality of inverters for forwarding an output signal from said first stage logic circuit to a succeeding stage and which is to become active when an activating signal is active. The device includes a threshold value correcting circuit formed by a threshold value correcting inverter and a switching circuit. The switching circuit connects an output terminal of the threshold value correcting inverter to an output terminal of the first stage logic circuit only during the period in which the activating signal is in its active state.

Abstract: A semiconductor memory device of the type having a pair of transfer gates between a bit line pair and an interconnection pair coupled to a sense amplifier circuit operates at a high speed because of the reduction of parasitic capacitances coupled to the sense amplifier circuit, however, the sense amplifier circuit is so sensitive to an electrical unbalance between the input nodes thereof that a transfer signal line is coupled to the gate electrodes of the transfer gates through a contact window located in such a manner that coupling capacitances between the transfer signal line and the interconnections do not provide the electrical unbalance, then the contact window is by way of example located between the interconnections.