Abstract: The present invention provides a method for treatment or prevention of cancer through novel action mechanism, namely, through inhibition of a riboflavin pathway. The method for treatment or prevention of cancer comprises administering an RF pathway inhibitor to a subject in need thereof.

Abstract: A programmable image processor capable of realizing a plurality of image formation operations is comprised of an SIMD type data operation processing section, RAMs, memory controllers, and memory switches. The memory controller and the memory switches selectively connect the plurality of RAMs to the data operation processing section thereby changing the memory capacity allotted to each image formation operation among a plurality of image formation operations.

Abstract: An image processor has a controller unit connected to at least one of functional units such as an image reading unit, detects a source of input of image data according to a network I/F or a parallel bus I/F. An image-memory access control section transmits the image data input from each of the functional units to a memory group and also transmits the image data stored in the memory group to the functional unit. A system controller controls the overall apparatus and also controls the image-memory access control section according to the input source of the image data to determine an order of transmitting the image data to the memory group.

Abstract: The image processing apparatus is provided with a plural memory controllers, each of which controls a RAM. The memory controllers are connected to an SIMD type arithmetic processing section. A control register is connected to the memory controllers. The control register controls transfer of image data between the RAMs and the SIMD type arithmetic processing section.

Abstract: An image processing apparatus is connected to a plurality of functional units including an image processor which processes images. A process controller provides control over the entire operation. A ROM previously stores information about the content of the image processing. The process controller reads the information stored in the ROM and transfers this information in a host buffer provided with the image processor. The image processor processes the image data based on the information stored in the host buffer.

Abstract: A programmable image processor capable of realizing a plurality of image formation operations is comprised of an SIMD type data operation processing section, RAMs, memory controllers, and memory switches. The memory controller and the memory switches selectively connect the plurality of RAMs to the data operation processing section thereby changing the memory capacity allotted to each image formation operation among a plurality of image formation operations.

Abstract: The image processing apparatus comprises an input I/F memory which reads pixels having a predetermined length, subjects the read pixels to buffering, and writes them in a SIMD type processor. The SIMD type processor performs batch processing of the pixels. Further, an output I/F memory reads the pixels batch-processed by the SIMD type processor, subjects the read pixels to buffering and writes them in a predetermined output destination. Read and/or write timing of IN—FIFO and OUT—FIFO is appropriately controlled.

Abstract: In the image processing apparatus, an image data control unit is connected to at least one of an image reading unit, an image memory control unit, an image processing unit, and an image writing unit. The image data control unit receives any one of an image data read by the image reading unit, image data read by the image memory control unit, and image data processed by the image processing unit. The image data control unit transmits the received image data to any of the image memory control unit, the image processing unit, and the image writing unit.

Abstract: A programmable image processor capable of realizing a plurality of image formation operations is comprised of an SIMD type data operation processing section, RAMs, memory controllers, and memory switches. The memory controller and the memory switches selectively connect the plurality of RAMs to the data operation processing section thereby changing the memory capacity allotted to each image formation operation among a plurality of image formation operations.

Abstract: In the image processing apparatus, an image data control unit is connected to at least one of an image reading unit, an image memory control unit, an image processing unit, and an image writing unit. The image data control unit receives any one of an image data read by the image reading unit, image data read by the image memory control unit, and image data processed by the image processing unit. The image data control unit transmits the received image data to any of the image memory control unit, the image processing unit, and the image writing unit.

Abstract: An image processor has a controller unit connected to at least one of functional units such as an image reading unit, detects a source of input of image data according to a network I/F or a parallel bus I/F. An image-memory access control section transmits the image data input from each of the functional units to a memory group and also transmits the image data stored in the memory group to the functional unit. A system controller controls the overall apparatus and also controls the image-memory access control section according to the input source of the image data to determine an order of transmitting the image data to the memory group.

Abstract: An image processor has a controller unit connected to at least one of functional units such as an image reading unit, detects a source of input of image data according to a network I/F or a parallel bus I/F. An image-memory access control section transmits the image data input from each of the functional units to a memory group and also transmits the image data stored in the memory group to the functional unit. A system controller controls the overall apparatus and also controls the image-memory access control section according to the input source of the image data to determine an order of transmitting the image data to the memory group.

Abstract: An image processor has a transfer control section that transfers a sequence of image processing and data for image processing to be added or updated from a host buffer to program RAM and data RAM. The host buffer receives the sequence of image processing and data for image processing to be added or updated transferred from a process controller, and temporarily stores the sequence and the data during idle cycle time that a processor array section does not execute image processing. The transfer control section provides controls for transfer so that the sequence of image processing and data for image processing to be added or updated are split into blocks for a plurality of transfer times, and the blocks are transferred from the host buffer to the program RAM and the data RAM.

Abstract: An image processor has a controller unit connected to at least one of functional units such as an image reading unit, detects a source of input of image data according to a network I/F or a parallel bus I/F. An image-memory access control section transmits the image data input from each of the functional units to a memory group and also transmits the image data stored in the memory group to the functional unit. A system controller controls the overall apparatus and also controls the image-memory access control section according to the input source of the image data to determine an order of transmitting the image data to the memory group.

Abstract: The image processing apparatus is provided with a plural memory controllers, each of which controls a RAM. The memory controllers are connected to an SIMD type arithmetic processing section. A control register is connected to the memory controllers. The control register controls transfer of image data between the RAMs and the SIMD type arithmetic processing section.

Abstract: A programmable image processor capable of realizing a plurality of image formation operations is comprised of an SIMD type data operation processing section, RAMs, memory controllers, and memory switches. The memory controller and the memory switches selectively connect the plurality of RAMs to the data operation processing section thereby changing the memory capacity allotted to each image formation operation among a plurality of image formation operations.

Abstract: An image processing apparatus including an image data input function for inputting image data, and an image output function for outputting data on which image processing has been, which comprises characteristic quantities from said image data input by said image data input function, and a control function for performing suitable image processing control of the input image data by fuzzy assumptions in accordance with the characteristic quantities.

Abstract: The apparatus provides a way of receiving graphic symbols whose sizes are mutually different, and whose positions are irregularly arranged, such as a handwritten flow chart. For example, the apparatus automatically generates a flow chart image in which sizes of the graphic symbols are adjusted to be balanced, and in which the positions of the centers of the graphic symbols are aligned. First, the apparatus transforms the input graphic image into vectors representing the graphic symbols. Then, a set of symbol parameters are recognized for each graphic symbol. Center positions of the groups of graphic symbols which fall within a predetermined range, are aligned. Also, the heights and widths of the group of graphic symbol are adjusted through use of the symbol parameters. Finally, aligned, size-adjusted graphic symbols are output in an output image.