Patents by Inventor Takako Shindo

Takako Shindo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for supporting verification, and computer product
    Patent number: 7676777
    Abstract: A verification support apparatus receives description data. Upon receiving the description data, the apparatus automatically generates and outputs a verification property, a verification scenario, specification data, review information, etc. In addition, the apparatus checks the description data for any element of deficiency or inconsistency before the automatic generation of the verification property. Therefore, the amount of description data can be reduced by sorting out the types of verification items and listing parameters, and various verification properties can be automatically generated by allowing a computer to read verification data. Furthermore, a design TAT can be reduced by generating the specification data. Furthermore, even a designer not familiar with a verification language such as PSL can easily execute assertion-based verification.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: March 9, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Satoshi Kowatari, Yoshiro Nakamura, Takako Shindo
  • Method and apparatus for supporting verification, and computer product
    Publication number: 20070234249
    Abstract: A verification support apparatus receives description data. Upon receiving the description data, the apparatus automatically generates and outputs a verification property, a verification scenario, specification data, review information, etc. In addition, the apparatus checks the description data for any element of deficiency or inconsistency before the automatic generation of the verification property. Therefore, the amount of description data can be reduced by sorting out the types of verification items and listing parameters, and various verification properties can be automatically generated by allowing a computer to read verification data. Furthermore, a design TAT can be reduced by generating the specification data. Furthermore, even a designer not familiar with a verification language such as PSL can easily execute assertion-based verification.
    Type: Application
    Filed: March 27, 2007
    Publication date: October 4, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Satoshi Kowatari, Yoshiro Nakamura, Takako Shindo