Patents by Inventor Takako Yoshihara

Takako Yoshihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7378732
    Abstract: A plurality of semiconductor packages is collectively fabricated on a wafer in a batch process and the wafer is then diced to obtain discrete semiconductor packages. The semiconductor package is a stacked body formed by bonding two or more semiconductor devices. Each semiconductor device comprises a substrate and a device pattern formed on a surface of the substrate. The semiconductor devices are stacked in such a fashion that a device pattern surface of the lower semiconductor device faces a non-device pattern surface of the semiconductor device stacked on the same.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: May 27, 2008
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takaharu Yamano, Takako Yoshihara, Masahiro Sunohara
  • Publication number: 20040207082
    Abstract: A plurality of semiconductor packages is collectively fabricated on a wafer in a batch process and the wafer is then diced to obtain discrete semiconductor packages. The semiconductor package is a stacked body formed by bonding two or more semiconductor devices. Each semiconductor device comprises a substrate and a device pattern formed on a surface of the substrate. The semiconductor devices are stacked in such a fashion that a device pattern surface of the lower semiconductor device faces a non-device pattern surface of the semiconductor device stacked on the same.
    Type: Application
    Filed: April 12, 2004
    Publication date: October 21, 2004
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takaharu Yamano, Takako Yoshihara, Masahiro Sunohara
  • Publication number: 20030094686
    Abstract: A semiconductor device comprises a semiconductor element having an electrode forming surface on which an electrode terminal is formed, an insulating layer made of phenol resin covering the electrode forming surface, and a rewiring pattern connected at one thereof to the electrode terminal and at the other end thereof to an external connecting terminal. During a process for manufacturing the phenol resin is cured at a temperature of 180° C. to 200° C. to form the insulating layer.
    Type: Application
    Filed: November 13, 2002
    Publication date: May 22, 2003
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takahiro Iijima, Akihito Takano, Takaharu Yamano, Takako Yoshihara, Yoshikatsu Seki