Abstract: A power source device has: a storage unit configured to receive a generated power and store as a storage power; a boost unit configured to generate, from a storage power supplied from the storage unit, a boosted power having a higher voltage than a voltage of the storage power, and supply the boosted power to a load; and a voltage detection unit configured to output a boost operation permission signal permitting a boost operation of the boost unit to the boost unit when the storage voltage of the boost unit increases to become a voltage equal to or higher than a minimum operation voltage of the boost unit. The boost unit is configured to start the boost operation by the storage power supplied from the storage unit and operates on the boosted power generated by the boost operation as an operation power source when the boost operation permission signal is output from the voltage detection unit.

Abstract: A boost DC-DC converter includes: an input terminal; an output terminal; a first boost circuit configured to generate, from an input power to the input terminal, a first boosted power having a higher voltage than a voltage of the input power, and outputs the generated first boosted power from the output terminal; a second boost circuit configured to generate, from the input power, a second boosted power having a higher voltage than the voltage of the input power; and a storage capacitor configured to store the second boosted power as a storage power, and supply the storage power to the first boost circuit as an operation power source. The first boost circuit is configured to start a boost operation with the storage power when a voltage of the storage power is equal to or higher than a minimum operation voltage of the first boost circuit.

Abstract: A power source device has: a storage unit configured to receive a generated power and store as a storage power; a boost unit configured to generate, from a storage power supplied from the storage unit, a boosted power having a higher voltage than a voltage of the storage power, and supply the boosted power to a load; and a voltage detection unit configured to output a boost operation permission signal permitting a boost operation of the boost unit to the boost unit when the storage voltage of the boost unit increases to become a voltage equal to or higher than a minimum operation voltage of the boost unit. The boost unit is configured to start the boost operation by the storage power supplied from the storage unit and operates on the boosted power generated by the boost operation as an operation power source when the boost operation permission signal is output from the voltage detection unit.

Abstract: An electronic device includes: a light detection circuit having a first light sensor and a second light sensor each generating a photocurrent by photoelectric conversion, a resistive element which allows a difference between the photocurrents generated by the first light sensor and the second light sensor to flow, and a voltage detection circuit which detects a voltage generated by the flow of the differential photocurrent through the resistive element, said electronic device being controlled in operation by an output signal of the light detection circuit; a storing unit charged each time the electronic device is operated; and a rectifying element provided between the storing unit and the resistive element. A current with which the storing unit is charged is made to flow to the resistive element through the rectifying element.

Abstract: An electronic device includes: a light detection circuit having a first light sensor and a second light sensor each generating a photocurrent by photoelectric conversion, a resistive element which allows a difference between the photocurrents generated by the first light sensor and the second light sensor to flow, and a voltage detection circuit which detects a voltage generated by the flow of the differential photocurrent through the resistive element, said electronic device being controlled in operation by an output signal of the light detection circuit; a storing unit charged each time the electronic device is operated; and a rectifying element provided between the storing unit and the resistive element. A current with which the storing unit is charged is made to flow to the resistive element through the rectifying element.

Abstract: Provided is an electronic device capable of supplying desired electric power to a load so as to operate the load even in a case where charged power is minute and a voltage increase rate of a capacitor, which increases by charge, is low. The electronic device includes: a power source which has supply power less than consumption power of the load; a capacitor to be charged with the supply power; and a charge/discharge control circuit which controls charging of the capacitor and consumption of charged power of the capacitor by the load, and the charge/discharge control circuit includes: a first node to which the supply power of the power source is supplied; and a circuit which charges the capacitor with the supply power from the first node.

Abstract: An invisible information embedding apparatus for embedding invisible information at a position in an obtained image includes an image analysis unit configured to obtain object information and positional information of an object included in the image, an embedding target image determining unit configured to determine whether the image is an embedding target based on the object information obtained by the image analysis unit, and an image synthesizing unit configured to combine the image with the invisible information based on the determination result of the embedding target image determining unit.

Abstract: Provided is an electronic device capable of supplying desired electric power to a load so as to operate the load even in a case where charged power is minute and a voltage increase rate of a capacitor, which increases by charge, is low. The electronic device includes: a power source which has supply power less than consumption power of the load; a capacitor to be charged with the supply power; and a charge/discharge control circuit which controls charging of the capacitor and consumption of charged power of the capacitor by the load, and the charge/discharge control circuit includes: a first node to which the supply power of the power source is supplied; and a circuit which charges the capacitor with the supply power from the first node.

Abstract: An invisible information embedding apparatus for embedding invisible information at a position in an obtained image includes an image analysis unit configured to obtain object information and positional information of an object included in the image, an embedding target image determining unit configured to determine whether the image is an embedding target based on the object information obtained by the image analysis unit, and an image synthesizing unit configured to combine the image with the invisible information based on the determination result of the embedding target image determining unit.

Abstract: To achieve a differential type logic circuit operating at a high speed and with a low voltage, the circuit is composed of a differential push-pull circuit comprising enhancement type NMOSFETs and depletion type NMOSFETs and a CMOS inverter pair circuit comprising inverters, and a threshold voltage of FETs of the CMOS inverter pair circuit is set to a value same as or greater than a threshold voltage of enhancement type FETs of the differential push-pull circuit and smaller than about ½ of supply voltage.

Abstract: A logic circuit having a first logic gate and remaining logic gate or gates. The first logic gate is interposed in a signal path determining an operating speed, and includes at least one first MOS transistor which has a threshold voltage lower than a predetermined voltage and operates at a high speed. The remaining logic gate or gates include at least one of a second MOS transistor and a third MOS transistor as a transistor having a margin for operating speed. The second MOS transistor has a middle threshold voltage equal to or greater than the predetermined voltage, and the third MOS transistor has a high threshold voltage equal to or greater than the predetermined voltage. The power consumption of the entire logic circuit at the time of operation is reduced, while maintaining the maximum operating speed.

Abstract: To achieve a differential type logic circuit operating at a high speed and with a low voltage, the circuit is composed of a differential push-pull circuit comprising enhancement type NMOSFETs and depletion type NMOSFETs and a CMOS inverter pair circuit comprising inverters, and a threshold voltage of FETs of the CMOS inverter pair circuit is set to a value same as or greater than a threshold voltage of enhancement type FETs of the differential push-pull circuit and smaller than about ½ of supply voltage.

Abstract: A self-timed pipelined datapath system reduces its power dissipation by accurately controlling the active and inactive states of the multi-threshold CMOS (MT-CMOS) circuit used as its combinational circuit. The MT-CMOS circuit comprises a logic circuit of low-threshold and a power control circuit formed of high-threshold transistors for controlling the power feeding to the logic circuit. The self-timed pipelined datapath system comprises: a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit for processing input data and a register connected to the input side of the combinational circuit; and an asynchronous signal control circuit that controls data transmission to and from each of the registers in the pipelined datapath circuit in response to a request signal.

Abstract: An adiabatic charging logic circuit includes a logic circuit and a power supply section. The logic circuit is constituted by a plurality of logic elements. The power supply section supplies power to the logic circuit to cause the logic circuit to perform logic processing after an input signal is supplied to the gate of each of the logic elements, and stops supply of the power before a new input signal is supplied to the gate of each of the logic elements after completion of the logic processing.

Abstract: A dynamic logic circuit comprising a plurality of unit dynamic logic circuits sequentially coupled in a multiple-stage fashion, each of which unit dynamic logic circuits including: a logic circuit portion formed by one or more than one MOS transistors; a first MOS transistor for a precharging or a pre-discharging operation with respect to the logic circuit; and a second MOS transistor to enable the logic circuit a discharging or a charging operation; wherein the MOS transistors composing the logic circuit portion are configured by low-threshold MOS transistors; and the second MOS transistor to enable the discharging or charging operation is composed of a high-threshold MOS transistor. The dynamic circuit is applied to a plural stage of combinational circuits in a self-timed pipelined datapath system, whereby a static leakage current at charging or pre-discharging operation can be reduced, resulting in decrease of power dissipation.

Abstract: A self-timed pipelined datapath system reduces its power dissipation by accurately controlling the active and inactive states of the multi-threshold CMOS (MT-CMOS) circuit used as its combinational circuit. The MT-CMOS circuit comprises a logic circuit of low-threshold and a power control circuit formed of high-threshold transistors for controlling the power feeding to the logic circuit. The self-timed pipelined datapath system comprises: a pipelined datapath circuit including a plurality of data processing stages, each having a combinational circuit for processing input data and a register connected to the input side of the combinational circuit; and an asynchronous signal control circuit that controls data transmission to and from each of the registers in the pipelined datapath circuit in response to a request signal.

Abstract: A logic circuit having a first logic gate and the remaining logic gate or gates. The first logic gate is interposed in a signal path determining an operating speed, and includes at least one first MOS transistor which has a threshold voltage lower than a predetermined voltage and operates at a high speed. The remaining logic gate or gates include at least one of a second MOS transistor and a third MOS transistor as a transistor having a margin for operating speed. The second MOS transistor has a middle threshold voltage equal to or greater than the predetermined voltage, and the third MOS transistor has a high threshold voltage equal to or greater than the predetermined voltage. The power consumption of the entire logic circuit at the time of operation is reduced, while maintaining the maximum operating speed.

Abstract: A MOSFET circuit achieving high speed operation and low power consumption for a wide supply voltage range. MOSFET circuits are connected between a low threshold voltage CMOS circuit and a supply voltage and ground, as a power controller for switching power supply in response to sleep/active modes. High threshold voltage MOSFETs in the MOSFET circuits are gate biased by low threshold voltage MOSFETs, thereby preventing a current from flowing across the backgate terminal and the source terminal.

Abstract: A SOI (Silicon On Insulator) logic circuit including serially connected power switching SOI MOSFETs (44, 45) and a logic circuit (43) constituted by SOI MOSFETs. The bodies of the MOSFETs of the logic circuit are made floating state, thereby implementing low threshold voltage MOSFETs. The bodies of the power switching MOSFETs are biased to power supply potentials, thereby implementing high threshold MOSFETs. The low threshold voltage MOSFETs enable the logic circuit to operate at a high speed in an active mode, and the high threshold voltage power switching MOSFETs can reduce the power dissipation in a sleep mode.

Abstract: A logic circuit includes a low-threshold logic circuit, a pair of first and second power lines, a first dummy power line, and a first high-frequency logic circuit. The low-threshold logic circuit has a logic circuit element constituted by a plurality of low-threshold field effect transistors. The pair of first and second power lines supply power to the low-threshold logic circuit. The first dummy power line is connected to one of power source terminals of the low-threshold logic circuit. The first high-threshold control transistor is arranged between the first dummy power line and the first power line.