Patents by Inventor Takamasa Chikuma

Takamasa Chikuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9318363
    Abstract: In STEP 1, a mapping operation is carried out by a mapping device. In STEP 2, based on position information for the wafer (W) detected by the mapping operation, it is determined whether or not a wafer (W) position is in an abnormal state or not. When the wafer position is determined to be in the abnormal state (Yes), a closing/opening operation, in which a FOUP door (19c) is temporarily closed and then opened, is carried out in STEP 3. In STEP 4, the number of times the FOUP door (19c) is closed/opened (in other words, the number of times a port door (62) is closed/opened) is counted, and in STEP 5, it is determined whether or not this count value is less than a preset value. If the count value is less than the preset value (Yes), the processing in STEP 1-STEP 5 is repeated once again.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: April 19, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kozo Kai, Takamasa Chikuma, Keiji Osada, Chunmui Li
  • Patent number: 9223305
    Abstract: A semiconductor manufacturing system includes circuitry configured to execute: displaying a screen for selecting an inspection set including inspection items having a manipulation item and/or a check item; retrieving the inspection items, arranging the inspection items in the order of workflow, and displaying each inspection item on a screen with an execution attribute indicating whether each inspection item is “automatic” or “manual” execution; receiving an inspection start command and reading the first inspection item from a storage unit. The circuitry also executes steps corresponding to the following cases (a) to (d) until there are no more inspection items: (a) the read-out inspection item being the manipulation item and “automatic”; (b) the read-out inspection item being the manipulation item and “manual”; (c) the read-out inspection item being the check item and “automatic”; and (d) the read-out inspection item being the check item and “manual”.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 29, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Gaku Ikeda, Koichi Miyashita, Takamasa Chikuma, Satoshi Gomi, Chunmui Li, Kunio Takano
  • Publication number: 20150005928
    Abstract: In STEP 1, a mapping operation is carried out by a mapping device. In STEP 2, based on position information for the wafer (W) detected by the mapping operation, it is determined whether or not a wafer (W) position is in an abnormal state or not. When the wafer position is determined to be in the abnormal state (Yes), a closing/opening operation, in which a FOUP door (19c) is temporarily closed and then opened, is carried out in STEP 3. In STEP 4, the number of times the FOUP door (19c) is closed/opened (in other words, the number of times a port door (62) is closed/opened) is counted, and in STEP 5, it is determined whether or not this count value is less than a preset value. If the count value is less than the preset value (Yes), the processing in STEP 1-STEP 5 is repeated once again.
    Type: Application
    Filed: January 8, 2013
    Publication date: January 1, 2015
    Inventors: Kozo Kai, Takamasa Chikuma, Keiji Osada, Chunmui Li
  • Publication number: 20130013240
    Abstract: A semiconductor manufacturing system includes a program for inspecting a device of the system executing: displaying a screen for selecting an inspection set including inspection items having a manipulation item and/or a check item; retrieving the inspection items, arranging the inspection items in the order of workflow, and displaying each inspection item on a screen with an execution attribute indicating whether each inspection item is “automatic” or “manual” execution; receiving an inspection start command and reading the first inspection item from a storage unit. The program also executes steps corresponding to the following cases (a) to (d) until there are no more inspection items: (a) the read-out inspection item being the manipulation item and “automatic”; (b) the read-out inspection item being the manipulation item and “manual”; (c) the read-out inspection item being the check item and “automatic”; and (d) the read-out inspection item being the check item and “manual”.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: TOKYO ELECTON LIMITED
    Inventors: Gaku Ikeda, Koichi Miyashita, Takamasa Chikuma, Satoshi Gomi, Chunmui Li, Kunio Takano
  • Patent number: 6999830
    Abstract: A method of processing a semiconductor wafer including the steps of executing a permutation processing by using a plurality of processing containers while sequentially transferring the wafers into the containers or performing a parallel processing and a transfer mechanism used commonly for the containers while sequentially transferring the wafers. The wafer processing is performed after the completion of conditioning of the vessel, and a conditioning start time for a next container is adjusted so that the completion of conditioning occurs when processing in the previous container is completed.
    Type: Grant
    Filed: November 29, 2002
    Date of Patent: February 14, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Shinji Arai, Takamasa Chikuma, Masahiro Mochizuki
  • Publication number: 20050015174
    Abstract: A method of processing a semiconductor wafer, characterized by comprising the steps of executing a permutation processing for processing (Pi) the semiconductor wafers by using a plurality of processing containers (A, B, C, D) for performing the processings different from each other while sequentially transferring (Ci) the wafers into the processing containers or performing a parallel processing for processing the wafers in the processing containers by using the plurality of processing containers for performing the processings identical to each other and a transfer mechanism used commonly for the processing containers while sequentially transferring the wafers into the processing containers by the transfer mechanism, wherein the processings of the wafers in the processing vessels are performed after the completion of the conditioning (Si) of the processing vessels and, in a first processing, a conditioning start time for a next processing container is adjusted so that the conditioning of the next processing co
    Type: Application
    Filed: November 29, 2002
    Publication date: January 20, 2005
    Inventors: Shinji Arai, Takamasa Chikuma, Masahiro Mochizuki