Abstract: A semiconductor device includes a first film that includes first electrode layers separated from each other in a first direction and extending in second and third directions, first columnar portions in the first film, that include a charge storage layer and a first semiconductor layer, and extend in the first direction, a second film on the first film and including second electrode layers separated from each other in the first direction and extending in second and third directions, second columnar portions in the second film and on the first columnar portions, that include a second semiconductor layer and extend in the first direction, and first insulating films separated from the second columnar portions in the third direction in the second film and extending in first and second directions. The first columnar portions form a square or rectangular lattice pattern below the first insulating films and a triangular lattice pattern elsewhere.

Abstract: A memory device includes first to third electrode layers and first to third columnar bodies. The first electrode layers are stacked above a foundation layer. The second and third electrode layers are arranged above the first electrode layers in a direction crossing a stacking direction of the first electrode layers. The first columnar body extends through the first and second electrode layers. The second columnar body extends through the first and third electrode layers. The third columnar body extends through the first electrode layers, and is positioned between the second electrode layer and the third electrode layer. The first to third columnar bodies include first to third semiconductor layers, respectively. The first and second semiconductor layers are electrically connected to the foundation layer, and the third semiconductor layer is electrically insulated from the foundation layer by an insulating film provided between the foundation layer and the third semiconductor layer.

Abstract: A semiconductor device includes a first film that includes first electrode layers separated from each other in a first direction and extending in second and third directions, first columnar portions in the first film, that include a charge storage layer and a first semiconductor layer, and extend in the first direction, a second film on the first film and including second electrode layers separated from each other in the first direction and extending in second and third directions, second columnar portions in the second film and on the first columnar portions, that include a second semiconductor layer and extend in the first direction, and first insulating films separated from the second columnar portions in the third direction in the second film and extending in first and second directions. The first columnar portions form a square or rectangular lattice pattern below the first insulating films and a triangular lattice pattern elsewhere.

Abstract: A memory device includes first to third electrode layers and first to third columnar bodies. The first electrode layers are stacked above a foundation layer. The second and third electrode layers are arranged above the first electrode layers in a direction crossing a stacking direction of the first electrode layers. The first columnar body extends through the first and second electrode layers. The second columnar body extends through the first and third electrode layers. The third columnar body extends through the first electrode layers, and is positioned between the second electrode layer and the third electrode layer. The first to third columnar bodies include first to third semiconductor layers, respectively. The first and second semiconductor layers are electrically connected to the foundation layer, and the third semiconductor layer is electrically insulated from the foundation layer by an insulating film provided between the foundation layer and the third semiconductor layer.

Abstract: A semiconductor memory device includes an interconnect layer including a conductive layer and a semiconductor layer of a first conductivity type provided on the conductive layer; a stacked body including a plurality of electrode layers stacked on the interconnect layer, a semiconductor pillar provided in the stacked body and extending through the plurality of electrode layers in a stacking direction thereof; and an insulating layer provided on the interconnect layer and extending along a lateral surface of the stacked body. The semiconductor layer includes a first semiconductor region of a second conductivity type positioned between the insulating layer and the conductive layer, and the first semiconductor region is in contact with the conductive layer.

Abstract: A semiconductor memory device includes an interconnect layer including a conductive layer and a semiconductor layer of a first conductivity type provided on the conductive layer; a stacked body including a plurality of electrode layers stacked on the interconnect layer, a semiconductor pillar provided in the stacked body and extending through the plurality of electrode layers in a stacking direction thereof; and an insulating layer provided on the interconnect layer and extending along a lateral surface of the stacked body. The semiconductor layer includes a first semiconductor region of a second conductivity type positioned between the insulating layer and the conductive layer, and the first semiconductor region is in contact with the conductive layer.

Abstract: According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction. A stepped wiring area includes a second conductive layer electrically connected to the first conductive layer. The second conductive layer has an end portion as a contact connection portion. A contact plug is connected to the contact connection portion. The contact plug extends in the laminating direction. The contact plug includes a first member and a second member. The first member extends in the laminating direction. The second member extends in a direction intersecting with the laminating direction inside the contact connection portion.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array which has: a first conductive layer which is arranged in a first direction on a first semiconductor layer; a second conductive layer which is arranged in the first direction above the first conductive layer; a columnar second semiconductor layer which extends in the first direction; and a contact unit which electrically connects the first semiconductor layer and the second conductive layer. The contact unit has a first film which contains silicide as a first metal, and is in contact with the first semiconductor layer; and a second film which contains the first metal, is in contact with the first film, and is in contact with the first semiconductor layer with the first film interposed therebetween.

Abstract: According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction. A stepped wiring area includes a second conductive layer electrically connected to the first conductive layer. The second conductive layer has an end portion as a contact connection portion. A contact plug is connected to the contact connection portion. The contact plug extends in the laminating direction. The contact plug includes a first member and a second member. The first member extends in the laminating direction. The second member extends in a direction intersecting with the laminating direction inside the contact connection portion.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array which has: a first conductive layer which is arranged in a first direction on a first semiconductor layer; a second conductive layer which is arranged in the first direction above the first conductive layer; a columnar second semiconductor layer which extends in the first direction; and a contact unit which electrically connects the first semiconductor layer and the second conductive layer. The contact unit has a first film which contains silicide as a first metal, and is in contact with the first semiconductor layer; and a second film which contains the first metal, is in contact with the first film, and is in contact with the first semiconductor layer with the first film interposed therebetween.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.

Abstract: A stacked body is disposed so as cover a periphery of a semiconductor columnar portion and includes a conductive layer and an inter-layer insulating layer stacked alternately in a stacking direction on a semiconductor substrate. An epitaxial layer is disposed on a surface of the semiconductor substrate and is electrically connected to a lower end of the semiconductor columnar portion. The semiconductor columnar portion comprises: an insulating film core; and a semiconductor portion disposed so as to cover a periphery of the insulating film core and electrically connected to the epitaxial layer at a lower end portion. The epitaxial layer includes a concave portion in a surface thereof, and the insulating film core has a lower end thereof positioned inside the concave portion.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.

Abstract: A semiconductor memory device according to an embodiment described below comprises: first lines arranged in a first direction perpendicular to a main surface of a substrate and extending in a second direction crossing the first direction; second lines arranged in the second direction, extending in the first direction, and intersecting the first lines; memory cells disposed at intersections of the first lines and the second lines; and an interlayer insulating film provided between the second lines. The interlayer insulating film has an air gap extending continuously in the first direction so as to intersect at least some of the first lines aligned along the first direction. The interlayer insulating film also includes an insulating film positioned above the air gap and having a curved surface that protrudes toward a direction of the substrate.

Abstract: This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.

Abstract: A semiconductor memory device comprises: first lines disposed in a first direction perpendicular to a substrate and extending in a second direction parallel to the substrate; second lines disposed in the second direction and configured to extend in the first direction, the second lines intersecting the first lines; and memory cells disposed at intersections of the first lines and the second lines and each including a variable resistance element. Furthermore, a third line extends in a third direction orthogonal to the first and second directions. A select transistor is connected between the second and third lines. A control circuit controls a voltage applied to the first and third lines, and the select transistor. The control circuit renders conductive at least one of the select transistors and thereby detect a current flowing in the third line, and determines a deterioration state of the select transistor according to a detection result.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a control circuit configured to cause data to be stored in a memory cell by setting the memory cell to be included in one of resistance value distributions. The control circuit is configured to set a first resistance value distribution and a second resistance value distribution, the second resistance value distribution having a resistance value larger than that of the first resistance value distribution, and to set a second width to be larger than a first width, the second width being a width between a second upper limit value of the second resistance value distribution and a second lower limit value of the second resistance value distribution, and the first width being a width between a first upper limit value of the first resistance value distribution and a first lower limit value of the first resistance value distribution.

Abstract: According to an embodiment, a non-volatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction orthogonal to the first direction. The device includes third wirings, and a first and a second memory. The third wirings extend in a third direction crossing the first direction and orthogonal to the second direction, and aligned in the second direction on both sides of the second wiring. The first memory is provided between one of third wiring pair and the second wiring, the pair of third wirings facing each other across the second wiring. The second memory is provided between another one of the third wiring pair and the second wiring. The second wiring has a block portion between a first portion in contact with the first memory and a second portion in contact with the second memory.

Abstract: First, a trench penetrating first conductive layers and interlayer insulating layers is formed. Next, a column-shaped conductive layer is formed to fill the trench via a side wall layer. Then, after formation of the side wall layer, by migration of oxygen atoms between the side wall layer and the first conductive layers or migration of oxygen atoms between the side wall layer and the interlayer insulating layers, a proportion of oxygen atoms in the side wall layer adjacent to the interlayer insulating layers is made larger than a proportion of oxygen atoms in the side wall layer adjacent to the first conductive layers, whereby the side wall layer adjacent to the first conductive layers is caused to function as the variable resistance element.