Abstract: The video signal processing circuit has a clamp circuit for clamping a composite video signal including a copy guard signal with amplitude of from white to black as well as a pseudo horizontal synchronization signal, a brilliant signal, and a synchronization signal. The circuit also has a synchronization signal separation circuit, which separates the synchronization signal from the composite video signal and a synchronization signal discrimination circuit, which identifies if the synchronization signal coming from the synchronization signal separation circuit has the same cycle as that of a horizontal synchronization signal, and which blocks the signal with the cycle shorter than the cycle of the horizontal synchronization signal, letting only the signal with the cycle of the horizontal synchronization signal pass.

Abstract: The keyed clamp circuit of this invention has the clamp circuit for clamping the video signal including the equalizing pulse and the vertical synchronization signal based on the clamp pulse, the synchronization signal separation circuit for separating the synchronization signal from the video signal clamped by the clamp circuit, and the clamp pulse generation circuit for generating the clamp pulse based on the synchronization signal from the synchronization signal separation circuit. The clamp pulse for the equaling pulse with a pulse width, which is shorter during the equalizing pulse period compared to the pulse width during the vertical synchronization signal period, is generated. The clamp pulse can be generated based on the equalizing pulse and the vertical synchronization signal, performing the keyed clamping on the video signal even during the blanking pulse period.

Abstract: The keyed clamp circuit of this invention has the clamp circuit for clamping the video signal including the equalizing pulse and the vertical synchronization signal based on the clamp pulse, the synchronization signal separation circuit for separating the synchronization signal from the video signal clamped by the clamp circuit, and the clamp pulse generation circuit for generating the clamp pulse based on the synchronization signal from the synchronization signal separation circuit. The clamp pulse for the equaling pulse with a pulse width, which is shorter during the equalizing pulse period compared to the pulse width during the vertical synchronization signal period, is generated. The clamp pulse can be generated based on the equalizing pulse and the vertical synchronization signal, performing the keyed clamping on the video signal even during the blanking pulse period.

Abstract: The video signal processing circuit has a clamp circuit for clamping a composite video signal including a copy guard signal with amplitude of from white to black as well as a pseudo horizontal synchronization signal, a brilliant signal, and a synchronization signal. The circuit also has a synchronization signal separation circuit, which separates the synchronization signal from the composite video signal and a synchronization signal discrimination circuit, which identifies if the synchronization signal coming from the synchronization signal separation circuit has the same cycle as that of a horizontal synchronization signal, and which blocks the signal with the cycle shorter than the cycle of the horizontal synchronization signal, letting only the signal with the cycle of the horizontal synchronization signal pass.